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constraint的on与off以及with约束
module crv; class PCIBus; rand bit[15:0] addr; rand bit[31:0] data; constraint addrw {addr[7:0] == 'h01;} constraint dataw {data[15:0] == 'hffff;} endclass logic [31:0] result; initial begin PCIBus pBus = new ( ); //I