ECE 510: Foundations

ECE 510：计算机工程基础
项目3
MIPS模拟器
这项作业将为您提供C ++编程和MIPS操作的经验。
流水线处理器。此外，您将深入了解如何并行发生多个事件
可以使用顺序机器进行仿真。
1.问题陈述
这种分配需要模拟一个简单的5级流水线机器。模拟器
应该能够逐周期实现MIPS体系结构。模拟器
关于寄存器的内容必须是周期精确的，但不必忠实于其他内容
硬件详细信息，例如控制信号。模拟器的输出，除了寄存器
内容和锁存器值应包括每个功能单元的利用率和
执行一组指令的总时间（以周期为单位）。根据
下面的C ++中描述的规范。提交代码，仿真结果和项目
说明文字。
1.1须执行的指示
模拟器应执行以下指令：加，减，加，mul，lw，sw，beq，lui，
and，andi或ori，sll，srl，slti和sltiu。请注意，这些指令操作整数指令
只要。 MIPS指令格式可用于除mul外的所有指令。假设语法
因为mul是mul $ a，$ b，$ c，这意味着我们将$ b和$ c的内容相乘，最低有效
结果的32位存放在寄存器$ a中，结果的最高32位将是
存储在寄存器$（a + 1）中。例如，mul $ t0，$ t8，$ t9将存储以下乘积的低32位：
$ t8 *寄存器$ t0中的$ t9和寄存器$ t1中乘积的高32位（提示：参见MIPS绿色
工作表说明摘要（寄存器编号）。这与多指令不同
在MIPS中。假定mul的操作码和功能代码与mult的操作码和功能代码相同。
1.2模拟器的输入
1）MIPS机器代码作为文本文件：通过以下方式将汇编级别的指令转换为机器级别
使用https://www.eg.bucknell.edu/~csci320/mips_web/或http://www.kurtm.net/mipsasm/
2）向用户查询以在指令模式还是循环模式之间进行选择
•指令模式：逐条指令观察程序指令的执行
•循环模式：逐周期观察程序的执行
3）向用户查询以选择指令数或循环数（取决于选择
在上一个查询中执行）。
4）在执行了用户最初输入的指令或周期数后，第三个
查询用户以选择是否继续执行。
•如果是，请从步骤3开始重复
•如果否，请退出执行并显示结果
1.3存储器，寄存器和PC
存储器为一个字宽，大小为2K字节。物理上有单独的说明，
用于指令和数据的数据存储器。数据存储器在开始时初始化为0
每次模拟运行。这台机器上没有缓存。
有32个寄存器；寄存器0硬接线为0。此外，还有一个程序计数器（PC）。
PC应该通过获取存储在其所在位置的指令来开始执行
初始化。
1.4 CPU
流水线式MIPS处理器具有5个阶段：IF，ID，EX，MEM，WB。有管道寄存器
在阶段之间：IF / ID，ID / EX，EX / MEM，MEM / WB。假设管道寄存器包含
以下闩锁：
•IF / ID：IR，NPC
•ID / EX：IR，NPC，A，B，Imm
•EX / MEM：IR，B，ALUOutput，cond
•MEM / WB：IR，ALUOutput，LMD
1.5模拟器的输出
除了在每次执行后显示寄存器内容和锁存值外
周期/指令，它应该输出以下统计数据
•每个阶段的利用。利用率是该阶段所在的周期的一部分
做有用的工作。只是在等待清除结构，控制或数据方面的危害
它的前面并不构成有用的工作。
•在仿真器上执行MIPS程序花费的总时间（以CPU周期为单位）
机器。 （这不是执行模拟所花费的时间；它是时间
被模拟的机器拍摄。）
1.6与分支机构打交道
处理器不执行分支预测。当ID阶段检测到分支时，它会询问
IF级停止读取并刷新IF_ID锁存器（插入NOP）。当EX阶段解决时
在分支中，根据分支结果，允许IF恢复取指令。
1.7其他说明
•无中断。
•不支持乱序执行
•不支持数据转发
•假设寄存器写操作在时钟周期的前半部分完成，并且寄存器读操作
在下半年进行。
•必须考虑所有数据，结构和控制危害。
•在EX阶段解析分支。
2.处理方式（建议ECE 510实验编程代写
首先弄清楚如何实现管道寄存器（建议使用类），

ECE 510: Foundations of Computer Engineering
Project 3
MIPS Simulator
This assignment will give you experience in programming in C++ and the operation of a MIPS
pipelined processor. Further, you will gain insight into how multiple events that occur in parallel
can be simulated using a sequential machine.
1. Problem Statement
This assignment requires a simple 5 stage pipelined machine to be simulated. The simulator
should be capable of implementing the MIPS architecture on a cycle by cycle basis. The simulator
must be cycle accurate with respect to contents of the registers, but need not be faithful to other
hardware details such as control signals. The output of the simulator, in addition to the register
contents and latch values should include the utilization factor of each functional unit and the
total time in cycles to execute a set of instructions. Implement the simulator according to the
specifications described below in C++. Submit the code, simulation results and a project
description write-up.
1.1 Instructions to be implemented
The simulator should implement the following instructions: add, sub, addi, mul, lw, sw, beq, lui,
and, andi, or, ori, sll, srl, slti, and sltiu. Note that these instructions operate integer instructions
only. The MIPS instruction format can be used for all instructions except mul. Assume the syntax
for mul is mul $a,$b,$c, meaning that we multiply the contents of $b and $c, the least significant
32 bits of results are placed in register $a and the most significant 32-bits of the result will be
stored in register $(a+1). For example, mul $t0, $t8, $t9 will store lower 32-bits of the product of
$t8 * $t9 in register $t0 and the upper 32-bits of the product in register $t1 (Hint: See MIPS green
sheet instructions summary for registers numbering). This is different from the mult instruction
in MIPS. Assume the opcode and function code for mul to be same as that of mult.
1.2 Inputs to the simulator
1) MIPS machine code as a text file: Convert the assembly level instructions to machine level by
using https://www.eg.bucknell.edu/~csci320/mips_web/ or http://www.kurtm.net/mipsasm/
2) A query to the user to select between instruction or cycle mode
• Instruction mode: To observe execution of the program instruction by instruction
• Cycle mode: To observe execution of the program cycle by cycle
3) A query to the user to select the number of instructions or cycles (depending on the choice
made in the previous query) to be executed.
4) After executing the number of instructions or cycles entered initially by the user, a third
query to the user to choose to continue execution or not.
• If yes, Repeat from step 3
• If no, exit the execution and display the results
1.3 Memory, Registers and PC
The memory is one word wide and 2K bytes in size. There are physically separate instruction and
data memories for the instruction and data. Data memory is initialized to 0 at the beginning of
each simulation run. There is no cache in this machine.
There are 32 registers; register 0 is hardwired to 0. In addition, there is a Program Counter (PC).
PC should start execution by fetching the instruction stored in the location to which it is
initialized.
1.4 CPU
The pipelined MIPS processor has 5 stages: IF, ID, EX, MEM, WB. There are pipeline registers
between the stages: IF/ID, ID/EX, EX/MEM, MEM/WB. Assume the pipeline registers to contain
following latches:
• IF/ID : IR, NPC
• ID/EX : IR, NPC, A, B , Imm
• EX/MEM : IR, B, ALUOutput , cond
• MEM/WB : IR, ALUOutput, LMD
1.5 Output of the simulator
In addition to displaying the register contents and latch values after the execution of each
cycle/instruction, it should output the following statistics
• Utilization of each stage. Utilization is the fraction of cycles for which the stage is
doing useful work. Just waiting for a structural, control, or data hazard to clear in
front of it does not constitute useful work.
• Total time (in CPU cycles) taken to execute the MIPS program on the simulated
machine. (This is NOT the time taken to execute the simulation; it is the time
taken by the machine being simulated.)
1.6 Dealing with branches
The processor does not implement branch prediction. When the ID stage detects a branch, it asks
the IF stage to stop fetching and flushes the IF_ID latch (inserts NOP). When the EX stage resolves
the branch, IF is allowed to resume instruction fetch depending on the branch outcome.
1.7 Other remarks
• No interrupts.
• Does not support out of order execution
• Does not support data forwarding
• Assume register writes are completed in the first half of clock cycle and register reads
are carried out in the second half.
• All data, structural and control hazards must be taken into account.
• Branches are resolved in the EX stage.
2. Way to approach (Suggestion)
Start by figuring out how to implement the Pipeline registers (use of class is recommended), the
5 stages of the pipeline, instruction and

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来源： https://www.cnblogs.com/hopjava/p/14613974.html