FPGA学习笔记17--always块产生波形

module test2; 

reg clk1,clk2; 

parameter CYCLE = 100; 

always 

   begin 

                    {clk1,clk2} = 2'b10; 

      #(CYCLE/4)  {clk1,clk2} = 2'b01; 

      #(CYCLE/4)  {clk1,clk2} = 2'b11; 

      #(CYCLE/4)  {clk1,clk2} = 2'b00; 

      #(CYCLE/4)  {clk1,clk2} = 2'b10; 

    end 

initial $monitor($time,,,"clk1=%b clk2=%b",clk1,clk2); 

endmodule 

标签：test2,FPGA,17,always,b10,clk1,clk2,CYCLE
来源： https://blog.csdn.net/weixin_43323123/article/details/104820925