[数字IC手撕verilog]脉冲同步、快到慢异步传输、开环闭环控制、握手反压

具体理论就不阐述了，只放代码和示意图建议直接看sunburst的cdc文章，不会出错

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

脉冲同步（开环控制）

 // a is faster than b, and a pulse is needed to tr
module pulse_cdc
(
	input clka,
  input clkb,
  input rst_n,
  
  input sig_a,
  output sig_b
);
  
  reg sig_a0, sig_b0, sig_b1, sig_b2;
  
  always @(posedge clka or negedge rst_n)begin
    if(!rst_n)
     	sig_a0 <= 1'b0;
    else if (sig_a)
      sig_a0 <= !sig_a0;
  end
  
  always @(posedge clkb or negedge rst_n)begin
    if(!rst_n)begin
      sig_b0 <= 1'b0;
      sig_b1 <= 1'b0;
      sig_b2 <= 1'b0;
    end
    else begin
      sig_b0 <= sig_a0;
      sig_b1 <= sig_b0;
      sig_b2 <= sig_b1;
    end
  end
  
  assign sig_b = sig_b2 ^ sig_b1;
endmodule

脉冲同步 握手反压

module pulse_cdc
(
	input clka,
	input clkb,
	input rst_n,
	input sig_a,
	output sig_b
);
  reg sig_a0, sig_a1, sig_a2;
  reg sig_b0, sig_b1, sig_b2;
  always @(posedge clka or negedge rst_n)begin
    if(!rst_n)
      sig_a0 <= 1'b0;
    else if (sig_a2 & ~sig_a) 	// 这里的条件其实是可以根据设计来的，也有直接写sig_a2的，具体要看输入sig_a脉冲的间隔
      sig_a0 <= 1'b0;
    else if (sig_a)
      sig_a0 <= 1'b1;
  end
  
  always @(posedge clkb or negedge rst_n)begin
    if(!rst_n)begin
      sig_b0 <= 1'b0;
    	sig_b1 <= 1'b0;
    end
    else begin
      sig_b0 <= sig_a0;
      sig_b1 <= sig_b0;
    end
  end
  
  always @(posedge clka or negedge rst_n)begin
    if(!rst_n)begin
      sig_a1 <= 1'b0;
      sig_a2 <= 1'b0;
    end
    else begin
      sig_a1 <= sig_b1;
      sig_a2 <= sig_a1;
    end
  end
  
  assign sig_b = sig_b1;
 
endmodule

标签：cdc,clka,反压,a0,sig,verilog,rst,input,IC
来源： https://www.cnblogs.com/pu1se/p/16551456.html