Verilog 练习 反相器

 代码如下

//2021-11-1
//反相器
`timescale 1ns/10ps
module inv(A,Y);
output Y;
input A;

assign Y=~A;

endmodule



//----testbench of inv------
module inv_tb;
reg aa;
wire yy;
inv  inv(.A(aa),.Y(yy));

initial begin
	aa=0;
	#10	aa=1;
	#10	aa=0;
	#10	aa=1;
	#10	$stop;
end 

endmodule

仿真结果如下

标签：aa,10,endmodule,inv,练习,module,Verilog,反相器
来源： https://blog.csdn.net/weixin_63090979/article/details/121090710