基于FPGA的自动售货机Verilog开发Modelsim仿真

部分参考代码

(末尾附文件)

module  Sell(
	input clk,
	input reset_n,
	
	input yiyuan_set,
	input wuyuan_set,
	input shiyuan_set,
	input ok_set_r,
	
	input [3:0] good_sel,
	input [7:0] good_price,
	
	output [3:0] current_price,
	output [3:0] current_num,
	output [3:0] money_shi,
	output [3:0] money_ge,
	
	output [3:0] final_num,
	
	output right_led,
	output wrong_led,
	output ok_set_vaild_r
);

reg right_led_r;
reg wrong_led_r;
reg ok_set_vaild;
reg [3:0] good_num_1;
reg [3:0] good_num_2;
reg [3:0] good_num_3;
reg [3:0] good_num_4;

reg [3:0] current_price_r;
reg [3:0] current_num_r;
reg [3:0] money_shi_r;
reg [3:0] money_ge_r;
reg [3:0] final_num_r;

reg [7:0] total;
reg [7:0] charge;

wire [3:0] total_ge;
wire [3:0] total_shi;
wire [3:0] total_bai;

wire [3:0] charge_ge;
wire [3:0] charge_shi;
wire [3:0] charge_bai;

BinToDec BinToDec_total(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(total),
		.one					(total_ge),
		.ten					(total_shi),
		.hun					(total_bai)
);

BinToDec BinToDec_charge(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(charge),
		.one					(charge_ge),
		.ten					(charge_shi),
		.hun					(charge_bai)
);

reg [6:0]	current_state, next_state;
parameter	IDLE = 7'd00,		
				M10 = 7'd10,				
			   M20 = 7'd20,			
				M30 = 7'd30,			
			   M40 = 7'd40,			
				M50 = 7'd50,			
			   M60 = 7'd60,
				M70 = 7'd70,
				M80 = 7'd80,
				M90 = 7'd90,
				M100 = 7'd100,
				M110 = 7'd110,
				M_OK = 7'd120,
				M_NEXT = 7'd121;
				
always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		current_state <= IDLE;
	else
		current_state <= next_state;
end

always@(yiyuan_set or wuyuan_set or shiyuan_set or ok_set_r) begin
	if(~reset_n) begin
		next_state <= IDLE;
	end
	
	else begin
		case(current_state)	
			IDLE:begin
				if(yiyuan_set)
					next_state <= M10;
				else if(wuyuan_set)
					next_state <= M50;
				else if(shiyuan_set)
					next_state <= M100;
				else
					next_state <= current_state;
			end
			
			M10:begin						
				if(yiyuan_set)
					next_state <= M20;
				else if(wuyuan_set)
					next_state <= M60;
				else
					next_state <= current_state;
			end
			
			M20:begin						
				if(yiyuan_set)
					next_state <= M30;
				else if(wuyuan_set)
					next_state <= M70;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
			
			M30:begin
				if(yiyuan_set)
					next_state <= M40;
				else if(wuyuan_set)
					next_state <= M80;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end

			M40:begin
				if(yiyuan_set)
					next_state <= M50;
				else if(wuyuan_set)
					next_state <= M90;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
			
			M50:begin
				if(yiyuan_set)
					next_state <= M60;
				else if(wuyuan_set)
					next_state <= M100;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
			
			M60:begin
				if(yiyuan_set)
					next_state <= M70;
				else if(wuyuan_set)
					next_state <= M110;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end			
			
			M70:begin
				if(yiyuan_set)
					next_state <= M80;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
			
			M80:begin
				if(yiyuan_set)
					next_state <= M90;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end

			M90:begin
				if(yiyuan_set)
					next_state <= M100;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
			
			M100:begin
				if(yiyuan_set)
					next_state <= M110;
				else if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
		
			M110:begin
				if(ok_set_r)
					next_state <= M_OK;
				else
					next_state <= current_state;
			end
			
			M_OK:begin
					next_state <= M_NEXT;			
			end
			
			M_NEXT:begin
				if(ok_set_r)
					next_state <= IDLE;
				else
					next_state <= current_state;
			end
			
			default:next_state <= IDLE;
		endcase
	end
end

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链接：https://pan.baidu.com/s/1Urjjsy4AAq2mesRCbH4JhQ
提取码：s1tv

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标签：FPGA,Modelsim,charge,num,自动售货机,output,input,total,reg
来源： https://blog.csdn.net/jianghuxiaoge/article/details/117379183