HDLBits Mt2015 q4

题目如下

该题其实有很多写法，但是我参考了别人的写法发现非常高效，同时也学到了新的代码思路，故做记录

题解如下

module top_module (input x, input y, output z);
    wire wire1,wire2,wire3,wire4;
    //--------------task A-------------------
    task A;
        input x,y;
        output z;
        
        z = (x ^ y) & x;
    endtask
    //------------------task B-----------------
    task B;
        input x,y;
        output z;
        
        z = (x == y)?1:0;
    endtask
    //---------------output---------------
    assign z = (wire1|wire2)^(wire3&wire4);
    always @(*)begin
        A(x,y,wire1);
        A(x,y,wire2);
        B(x,y,wire3);
        B(x,y,wire4);
    end
    
endmodule

标签：wire2,task,wire4,q4,HDLBits,wire3,Mt2015,output,input
来源： https://blog.csdn.net/qq_37858023/article/details/116278854