github上点赞前100的UVM仓库
作者：互联网
| NAME | OWNER | STAR | URL | DESCRIPTION |
|---|---|---|---|---|
| uvmprimer | raysalemi | 174 | SystemVerilog | https://github.com/raysalemi/uvmprimer |
| logic | tymonx | 136 | SystemVerilog | https://github.com/tymonx/logic |
| UVMReference | VerificationExcellence | 110 | SystemVerilog | https://github.com/VerificationExcellence/UVMReference |
| uvm-tutorial-for-candy-lovers | cluelogic | 79 | SystemVerilog | https://github.com/cluelogic/uvm-tutorial-for-candy-lovers |
| svaunit | amiq-consulting | 49 | SystemVerilog | https://github.com/amiq-consulting/svaunit |
| tvip-axi | taichi-ishitani | 47 | SystemVerilog | https://github.com/taichi-ishitani/tvip-axi |
| AHB2 | GodelMachine | 43 | SystemVerilog | https://github.com/GodelMachine/AHB2 |
| uvm_agents | dovstamler | 41 | SystemVerilog | https://github.com/dovstamler/uvm_agents |
| UVM | mayurkubavat | 38 | SystemVerilog | https://github.com/mayurkubavat/UVM |
| tnoc | taichi-ishitani | 37 | SystemVerilog | https://github.com/taichi-ishitani/tnoc |
| combinator-uvm | doswellf | 27 | SystemVerilog | https://github.com/doswellf/combinator-uvm |
| axi-uvm | marcoz001 | 23 | SystemVerilog | https://github.com/marcoz001/axi-uvm |
| custom_uvm_report_server | kaushalmodi | 18 | SystemVerilog | https://github.com/kaushalmodi/custom_uvm_report_server |
| uvm-utest | nosnhojn | 17 | SystemVerilog | https://github.com/nosnhojn/uvm-utest |
| AMBA_APB_SRAM | courageheart | 16 | SystemVerilog | https://github.com/courageheart/AMBA_APB_SRAM |
| ISP_UVM | nelsoncsc | 15 | SystemVerilog | https://github.com/nelsoncsc/ISP_UVM |
| second_edition | advanced-uvm | 15 | SystemVerilog | https://github.com/advanced-uvm/second_edition |
| uvm_debug | uvmdebug | 13 | SystemVerilog | https://github.com/uvmdebug/uvm_debug |
| easyUVM | nelsoncsc | 13 | SystemVerilog | https://github.com/nelsoncsc/easyUVM |
| UVM | chiggs | 12 | SystemVerilog | https://github.com/chiggs/UVM |
| uvm_apb | smartfoxdata | 12 | SystemVerilog | https://github.com/smartfoxdata/uvm_apb |
| uvm_gen | hjking | 11 | SystemVerilog | https://github.com/hjking/uvm_gen |
| uvm-components | pulp-platform | 11 | SystemVerilog | https://github.com/pulp-platform/uvm-components |
| uvm_candy_lover | zhajio1988 | 10 | SystemVerilog | https://github.com/zhajio1988/uvm_candy_lover |
| ref-uvm-i2c-wb | ic7x24 | 10 | SystemVerilog | https://github.com/ic7x24/ref-uvm-i2c-wb |
| jarvisuk | shady831213 | 9 | SystemVerilog | https://github.com/shady831213/jarvisuk |
| freecellera-uvm | Freecellera | 8 | SystemVerilog | https://github.com/Freecellera/freecellera-uvm |
| RISC_VERIF_DEMO_0 | MushroomZQ | 8 | SystemVerilog | https://github.com/MushroomZQ/RISC_VERIF_DEMO_0 |
| uvm_reg_to_ipxact | amiq-consulting | 8 | SystemVerilog | https://github.com/amiq-consulting/uvm_reg_to_ipxact |
| uvm_axi | smartfoxdata | 8 | SystemVerilog | https://github.com/smartfoxdata/uvm_axi |
| uvm_axi4lite | smartfoxdata | 8 | SystemVerilog | https://github.com/smartfoxdata/uvm_axi4lite |
| uvm | accellera | 7 | SystemVerilog | https://github.com/accellera/uvm |
| ahb3_uvm_tb | designsolver | 7 | SystemVerilog | https://github.com/designsolver/ahb3_uvm_tb |
| yuu_ahb | seabeam | 7 | SystemVerilog | https://github.com/seabeam/yuu_ahb |
| uvm_starter | smartfoxdata | 7 | SystemVerilog | https://github.com/smartfoxdata/uvm_starter |
| YasaUvk | zhajio1988 | 7 | SystemVerilog | https://github.com/zhajio1988/YasaUvk |
| AHB-APB_Bridge_UVM_Env | Gateway91 | 6 | SystemVerilog | https://github.com/Gateway91/AHB-APB_Bridge_UVM_Env |
| UVM-APB_RAL | JoseIuri | 5 | SystemVerilog | https://github.com/JoseIuri/UVM-APB_RAL |
| yamm | amiq-consulting | 5 | SystemVerilog | https://github.com/amiq-consulting/yamm |
| Gaia | GeraltShi | 5 | SystemVerilog | https://github.com/GeraltShi/Gaia |
| gpio_agent | imokanj | 5 | SystemVerilog | https://github.com/imokanj/gpio_agent |
| uvm_sin_cos_table | vlotnik | 5 | SystemVerilog | https://github.com/vlotnik/uvm_sin_cos_table |
| UVM-Verification-Testbench-For-SimpleBus | rdou | 5 | SystemVerilog | https://github.com/rdou/UVM-Verification-Testbench-For-SimpleBus |
| yuu_apb | seabeam | 5 | SystemVerilog | https://github.com/seabeam/yuu_apb |
| regModel | briandong | 5 | SystemVerilog | https://github.com/briandong/regModel |
| sva_traces | go2uvm | 5 | SystemVerilog | https://github.com/go2uvm/sva_traces |
| uvm_agent_gen | blargony | 4 | SystemVerilog | https://github.com/blargony/uvm_agent_gen |
| i2c_wb_sv_uvm | rajkumarraval | 4 | SystemVerilog | https://github.com/rajkumarraval/i2c_wb_sv_uvm |
| UVM-Simulation-JTAG | serinvarghese | 4 | SystemVerilog | https://github.com/serinvarghese/UVM-Simulation-JTAG |
| UART | darthsider | 4 | SystemVerilog | https://github.com/darthsider/UART |
| UvmEnvUartApb | nguyenquanicd | 4 | SystemVerilog | https://github.com/nguyenquanicd/UvmEnvUartApb |
| tue | taichi-ishitani | 4 | SystemVerilog | https://github.com/taichi-ishitani/tue |
| uvmgen | edcote | 4 | SystemVerilog | https://github.com/edcote/uvmgen |
| cagt | amiq-consulting | 4 | SystemVerilog | https://github.com/amiq-consulting/cagt |
| UVM_Verification | avashist003 | 4 | SystemVerilog | https://github.com/avashist003/UVM_Verification |
| tvip-apb | taichi-ishitani | 4 | SystemVerilog | https://github.com/taichi-ishitani/tvip-apb |
| uvm_auto | mingzhang952 | 3 | SystemVerilog | https://github.com/mingzhang952/uvm_auto |
| uart2bustestbench | hanysalah | 3 | SystemVerilog | https://github.com/hanysalah/uart2bustestbench |
| uvm-phase-jumping | PedroHSCavalcante | 3 | SystemVerilog | https://github.com/PedroHSCavalcante/uvm-phase-jumping |
| UVM-Verification-Testbench-For-FIFO | rdou | 3 | SystemVerilog | https://github.com/rdou/UVM-Verification-Testbench-For-FIFO |
| uvm | kippy620 | 3 | SystemVerilog | https://github.com/kippy620/uvm |
| Async_FIFO_Verification | akzare | 3 | SystemVerilog | https://github.com/akzare/Async_FIFO_Verification |
| uvmBasics | adibis | 3 | SystemVerilog | https://github.com/adibis/uvmBasics |
| yuu_vip_gen | seabeam | 3 | SystemVerilog | https://github.com/seabeam/yuu_vip_gen |
| UVM_primer | hmomkar | 3 | SystemVerilog | https://github.com/hmomkar/UVM_primer |
| sv_practice | harpreetbhatia | 3 | SystemVerilog | https://github.com/harpreetbhatia/sv_practice |
| RISCV-UVM-Verification | vatsal184 | 3 | SystemVerilog | https://github.com/vatsal184/RISCV-UVM-Verification |
| A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM | alice820621 | 3 | SystemVerilog | https://github.com/alice820621/A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM |
| async_FIFO | dadongshangu | 3 | SystemVerilog | https://github.com/dadongshangu/async_FIFO |
| wishbone_uvc | alexzhang007 | 3 | SystemVerilog | https://github.com/alexzhang007/wishbone_uvc |
| yuu_clock | seabeam | 3 | SystemVerilog | https://github.com/seabeam/yuu_clock |
| uvm | aravindprakash | 2 | SystemVerilog | https://github.com/aravindprakash/uvm |
| uvm | SymbiFlow | 2 | SystemVerilog | https://github.com/SymbiFlow/uvm |
| UVM_Python_UVMC | JoseIuri | 2 | SystemVerilog | https://github.com/JoseIuri/UVM_Python_UVMC |
| MAC_BFM | jchengX | 2 | SystemVerilog | https://github.com/jchengX/MAC_BFM |
| uvm_lab | chenfengrugao | 2 | SystemVerilog | https://github.com/chenfengrugao/uvm_lab |
| uvm_testbench | mowsong | 2 | SystemVerilog | https://github.com/mowsong/uvm_testbench |
| UVM_UART_Example | WeiChungWu | 2 | SystemVerilog | https://github.com/WeiChungWu/UVM_UART_Example |
| apb_uvm | chan-henry | 2 | SystemVerilog | https://github.com/chan-henry/apb_uvm |
| uvm-templates | nbrummel | 2 | SystemVerilog | https://github.com/nbrummel/uvm-templates |
| UVM_verification | ganesh-ps | 2 | SystemVerilog | https://github.com/ganesh-ps/UVM_verification |
| SimpleAdder-UVM | tamannarupani | 2 | SystemVerilog | https://github.com/tamannarupani/SimpleAdder-UVM |
| uvm-indirect-registers | uwesimm | 2 | SystemVerilog | https://github.com/uwesimm/uvm-indirect-registers |
| ExtremeDV_UVM | zhajio1988 | 2 | SystemVerilog | https://github.com/zhajio1988/ExtremeDV_UVM |
| MPSoC-DV | PacoReinaCampo | 2 | SystemVerilog | https://github.com/PacoReinaCampo/MPSoC-DV |
| cpu | kruegz | 2 | SystemVerilog | https://github.com/kruegz/cpu |
| UVM-Verification-Testbench-For-APB | rdou | 2 | SystemVerilog | https://github.com/rdou/UVM-Verification-Testbench-For-APB |
| UVM-Testbench-for-Flex-Timer | hrishikeshpujari | 2 | SystemVerilog | https://github.com/hrishikeshpujari/UVM-Testbench-for-Flex-Timer |
| UART-16550 | Shivanagender123 | 2 | SystemVerilog | https://github.com/Shivanagender123/UART-16550 |
| SoC-DV | PacoReinaCampo | 2 | SystemVerilog | https://github.com/PacoReinaCampo/SoC-DV |
| AHB_APB-Bridge | Shivanagender123 | 2 | SystemVerilog | https://github.com/Shivanagender123/AHB_APB-Bridge |
| Shift_Register | Shivanagender123 | 2 | SystemVerilog | https://github.com/Shivanagender123/Shift_Register |
| uvm | akilystic | 1 | SystemVerilog | https://github.com/akilystic/uvm |
| UVM | tyxuanyuanlx | 1 | SystemVerilog | https://github.com/tyxuanyuanlx/UVM |
| AHB-with-FIFO | Emi-Pushpam | 1 | SystemVerilog | https://github.com/Emi-Pushpam/AHB-with-FIFO |
| basic_uvmc_oct | nelsoncsc | 1 | SystemVerilog | https://github.com/nelsoncsc/basic_uvmc_oct |
| uvm_ahb_lite | zhelnio | 1 | SystemVerilog | https://github.com/zhelnio/uvm_ahb_lite |
| SMC_Verification | fifthheaven | 1 | SystemVerilog | https://github.com/fifthheaven/SMC_Verification |
| uvm_objections | dcblack | 1 | SystemVerilog | https://github.com/dcblack/uvm_objections |
| apb_vip | asveske | 1 | SystemVerilog | https://github.com/asveske/apb_vip |
标签：github,UVM,Testbench,APB,100,com,uvm 来源： https://blog.csdn.net/zhajio/article/details/110846081