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github上点赞前100的UVM仓库

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NAMEOWNERSTARURLDESCRIPTION
uvmprimerraysalemi174SystemVeriloghttps://github.com/raysalemi/uvmprimer
logictymonx136SystemVeriloghttps://github.com/tymonx/logic
UVMReferenceVerificationExcellence110SystemVeriloghttps://github.com/VerificationExcellence/UVMReference
uvm-tutorial-for-candy-loverscluelogic79SystemVeriloghttps://github.com/cluelogic/uvm-tutorial-for-candy-lovers
svaunitamiq-consulting49SystemVeriloghttps://github.com/amiq-consulting/svaunit
tvip-axitaichi-ishitani47SystemVeriloghttps://github.com/taichi-ishitani/tvip-axi
AHB2GodelMachine43SystemVeriloghttps://github.com/GodelMachine/AHB2
uvm_agentsdovstamler41SystemVeriloghttps://github.com/dovstamler/uvm_agents
UVMmayurkubavat38SystemVeriloghttps://github.com/mayurkubavat/UVM
tnoctaichi-ishitani37SystemVeriloghttps://github.com/taichi-ishitani/tnoc
combinator-uvmdoswellf27SystemVeriloghttps://github.com/doswellf/combinator-uvm
axi-uvmmarcoz00123SystemVeriloghttps://github.com/marcoz001/axi-uvm
custom_uvm_report_serverkaushalmodi18SystemVeriloghttps://github.com/kaushalmodi/custom_uvm_report_server
uvm-utestnosnhojn17SystemVeriloghttps://github.com/nosnhojn/uvm-utest
AMBA_APB_SRAMcourageheart16SystemVeriloghttps://github.com/courageheart/AMBA_APB_SRAM
ISP_UVMnelsoncsc15SystemVeriloghttps://github.com/nelsoncsc/ISP_UVM
second_editionadvanced-uvm15SystemVeriloghttps://github.com/advanced-uvm/second_edition
uvm_debuguvmdebug13SystemVeriloghttps://github.com/uvmdebug/uvm_debug
easyUVMnelsoncsc13SystemVeriloghttps://github.com/nelsoncsc/easyUVM
UVMchiggs12SystemVeriloghttps://github.com/chiggs/UVM
uvm_apbsmartfoxdata12SystemVeriloghttps://github.com/smartfoxdata/uvm_apb
uvm_genhjking11SystemVeriloghttps://github.com/hjking/uvm_gen
uvm-componentspulp-platform11SystemVeriloghttps://github.com/pulp-platform/uvm-components
uvm_candy_loverzhajio198810SystemVeriloghttps://github.com/zhajio1988/uvm_candy_lover
ref-uvm-i2c-wbic7x2410SystemVeriloghttps://github.com/ic7x24/ref-uvm-i2c-wb
jarvisukshady8312139SystemVeriloghttps://github.com/shady831213/jarvisuk
freecellera-uvmFreecellera8SystemVeriloghttps://github.com/Freecellera/freecellera-uvm
RISC_VERIF_DEMO_0MushroomZQ8SystemVeriloghttps://github.com/MushroomZQ/RISC_VERIF_DEMO_0
uvm_reg_to_ipxactamiq-consulting8SystemVeriloghttps://github.com/amiq-consulting/uvm_reg_to_ipxact
uvm_axismartfoxdata8SystemVeriloghttps://github.com/smartfoxdata/uvm_axi
uvm_axi4litesmartfoxdata8SystemVeriloghttps://github.com/smartfoxdata/uvm_axi4lite
uvmaccellera7SystemVeriloghttps://github.com/accellera/uvm
ahb3_uvm_tbdesignsolver7SystemVeriloghttps://github.com/designsolver/ahb3_uvm_tb
yuu_ahbseabeam7SystemVeriloghttps://github.com/seabeam/yuu_ahb
uvm_startersmartfoxdata7SystemVeriloghttps://github.com/smartfoxdata/uvm_starter
YasaUvkzhajio19887SystemVeriloghttps://github.com/zhajio1988/YasaUvk
AHB-APB_Bridge_UVM_EnvGateway916SystemVeriloghttps://github.com/Gateway91/AHB-APB_Bridge_UVM_Env
UVM-APB_RALJoseIuri5SystemVeriloghttps://github.com/JoseIuri/UVM-APB_RAL
yammamiq-consulting5SystemVeriloghttps://github.com/amiq-consulting/yamm
GaiaGeraltShi5SystemVeriloghttps://github.com/GeraltShi/Gaia
gpio_agentimokanj5SystemVeriloghttps://github.com/imokanj/gpio_agent
uvm_sin_cos_tablevlotnik5SystemVeriloghttps://github.com/vlotnik/uvm_sin_cos_table
UVM-Verification-Testbench-For-SimpleBusrdou5SystemVeriloghttps://github.com/rdou/UVM-Verification-Testbench-For-SimpleBus
yuu_apbseabeam5SystemVeriloghttps://github.com/seabeam/yuu_apb
regModelbriandong5SystemVeriloghttps://github.com/briandong/regModel
sva_tracesgo2uvm5SystemVeriloghttps://github.com/go2uvm/sva_traces
uvm_agent_genblargony4SystemVeriloghttps://github.com/blargony/uvm_agent_gen
i2c_wb_sv_uvmrajkumarraval4SystemVeriloghttps://github.com/rajkumarraval/i2c_wb_sv_uvm
UVM-Simulation-JTAGserinvarghese4SystemVeriloghttps://github.com/serinvarghese/UVM-Simulation-JTAG
UARTdarthsider4SystemVeriloghttps://github.com/darthsider/UART
UvmEnvUartApbnguyenquanicd4SystemVeriloghttps://github.com/nguyenquanicd/UvmEnvUartApb
tuetaichi-ishitani4SystemVeriloghttps://github.com/taichi-ishitani/tue
uvmgenedcote4SystemVeriloghttps://github.com/edcote/uvmgen
cagtamiq-consulting4SystemVeriloghttps://github.com/amiq-consulting/cagt
UVM_Verificationavashist0034SystemVeriloghttps://github.com/avashist003/UVM_Verification
tvip-apbtaichi-ishitani4SystemVeriloghttps://github.com/taichi-ishitani/tvip-apb
uvm_automingzhang9523SystemVeriloghttps://github.com/mingzhang952/uvm_auto
uart2bustestbenchhanysalah3SystemVeriloghttps://github.com/hanysalah/uart2bustestbench
uvm-phase-jumpingPedroHSCavalcante3SystemVeriloghttps://github.com/PedroHSCavalcante/uvm-phase-jumping
UVM-Verification-Testbench-For-FIFOrdou3SystemVeriloghttps://github.com/rdou/UVM-Verification-Testbench-For-FIFO
uvmkippy6203SystemVeriloghttps://github.com/kippy620/uvm
Async_FIFO_Verificationakzare3SystemVeriloghttps://github.com/akzare/Async_FIFO_Verification
uvmBasicsadibis3SystemVeriloghttps://github.com/adibis/uvmBasics
yuu_vip_genseabeam3SystemVeriloghttps://github.com/seabeam/yuu_vip_gen
UVM_primerhmomkar3SystemVeriloghttps://github.com/hmomkar/UVM_primer
sv_practiceharpreetbhatia3SystemVeriloghttps://github.com/harpreetbhatia/sv_practice
RISCV-UVM-Verificationvatsal1843SystemVeriloghttps://github.com/vatsal184/RISCV-UVM-Verification
A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFMalice8206213SystemVeriloghttps://github.com/alice820621/A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
async_FIFOdadongshangu3SystemVeriloghttps://github.com/dadongshangu/async_FIFO
wishbone_uvcalexzhang0073SystemVeriloghttps://github.com/alexzhang007/wishbone_uvc
yuu_clockseabeam3SystemVeriloghttps://github.com/seabeam/yuu_clock
uvmaravindprakash2SystemVeriloghttps://github.com/aravindprakash/uvm
uvmSymbiFlow2SystemVeriloghttps://github.com/SymbiFlow/uvm
UVM_Python_UVMCJoseIuri2SystemVeriloghttps://github.com/JoseIuri/UVM_Python_UVMC
MAC_BFMjchengX2SystemVeriloghttps://github.com/jchengX/MAC_BFM
uvm_labchenfengrugao2SystemVeriloghttps://github.com/chenfengrugao/uvm_lab
uvm_testbenchmowsong2SystemVeriloghttps://github.com/mowsong/uvm_testbench
UVM_UART_ExampleWeiChungWu2SystemVeriloghttps://github.com/WeiChungWu/UVM_UART_Example
apb_uvmchan-henry2SystemVeriloghttps://github.com/chan-henry/apb_uvm
uvm-templatesnbrummel2SystemVeriloghttps://github.com/nbrummel/uvm-templates
UVM_verificationganesh-ps2SystemVeriloghttps://github.com/ganesh-ps/UVM_verification
SimpleAdder-UVMtamannarupani2SystemVeriloghttps://github.com/tamannarupani/SimpleAdder-UVM
uvm-indirect-registersuwesimm2SystemVeriloghttps://github.com/uwesimm/uvm-indirect-registers
ExtremeDV_UVMzhajio19882SystemVeriloghttps://github.com/zhajio1988/ExtremeDV_UVM
MPSoC-DVPacoReinaCampo2SystemVeriloghttps://github.com/PacoReinaCampo/MPSoC-DV
cpukruegz2SystemVeriloghttps://github.com/kruegz/cpu
UVM-Verification-Testbench-For-APBrdou2SystemVeriloghttps://github.com/rdou/UVM-Verification-Testbench-For-APB
UVM-Testbench-for-Flex-Timerhrishikeshpujari2SystemVeriloghttps://github.com/hrishikeshpujari/UVM-Testbench-for-Flex-Timer
UART-16550Shivanagender1232SystemVeriloghttps://github.com/Shivanagender123/UART-16550
SoC-DVPacoReinaCampo2SystemVeriloghttps://github.com/PacoReinaCampo/SoC-DV
AHB_APB-BridgeShivanagender1232SystemVeriloghttps://github.com/Shivanagender123/AHB_APB-Bridge
Shift_RegisterShivanagender1232SystemVeriloghttps://github.com/Shivanagender123/Shift_Register
uvmakilystic1SystemVeriloghttps://github.com/akilystic/uvm
UVMtyxuanyuanlx1SystemVeriloghttps://github.com/tyxuanyuanlx/UVM
AHB-with-FIFOEmi-Pushpam1SystemVeriloghttps://github.com/Emi-Pushpam/AHB-with-FIFO
basic_uvmc_octnelsoncsc1SystemVeriloghttps://github.com/nelsoncsc/basic_uvmc_oct
uvm_ahb_litezhelnio1SystemVeriloghttps://github.com/zhelnio/uvm_ahb_lite
SMC_Verificationfifthheaven1SystemVeriloghttps://github.com/fifthheaven/SMC_Verification
uvm_objectionsdcblack1SystemVeriloghttps://github.com/dcblack/uvm_objections
apb_vipasveske1SystemVeriloghttps://github.com/asveske/apb_vip

标签:github,UVM,Testbench,APB,100,com,uvm
来源: https://blog.csdn.net/zhajio/article/details/110846081