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SVRF 学习笔记

作者:互联网

https://www.cnblogs.com/yeungchie/

Typical IC Design and Verification Flow(标准的 IC 设计和验证流程)

graph TD sch(Source Netlist) sim(Simulation) apr(Automated Layout) anaologlayout(Full Custom Editing) top(Layout) verify(Layout Verification) tapeout(Pattern Generation) sch --> sim sim --> apr --> top sim --> anaologlayout --> top top --> verify verify --> tapeout verify --> sch

What is a SVRF File ?

What Are Operations ?

Operations work on the layout data:(对 Layout 数据起作用)

What Are Specification Statements ?

How Do I Create a Rule File ?

Rule File Compilation

If you have a compilation failure, the error is reported.(如果编译失败,将报告错误)
Fix the error and run Calibre again.(修正错误并再次运行 Calibre )
Repeat this process until you get a successful run.(重复此过程,直到成功运行)

标签:Layer,Layout,--,Calibre,rule,学习,笔记,file,SVRF
来源: https://www.cnblogs.com/yeungchie/p/13772651.html