编写Verilog时应注意：
1.不同always中不能同时对相同的reg赋值
2.如需将输入端口wire型变量读入，需要将其在always语句中存储到reg变量中
3.always@() begin reg1<=wire+reg1;reg1<=wire+wire;reg1<=reg1+reg2;
end
标签：wire,变量,always,reg1,语法,verilog,reg,Verilog
来源： https://www.cnblogs.com/amxiang/p/13658018.html