一種W1C類型Register的RTL實現方法

       前言：在Design中會用到很多的states寄存器，用來指示Design的工作狀態，而Sofeware可以通過設置其他寄存器來清除掉這些States，這種需求可以用W1C類型（寫1清0，讀取無影響，寫0無影響）的寄存器來實現。

一、定義偏移地址（offset）

localparam    RG_ERR_FLAG_HP    =    12'h80;
localparam    RG_ERR_FLAG_LP    =    12'h84;

二、寫使能信號的邏輯

wire    apb_wr_ps;
wire    apb_rd_ps;
wire    apb_rd_en;

assign  apb_wr_ps = psel_wr & pwrite_wr  & penable_wr;
assign  apb_rd_ps = psel_rd & ~pwrite_rd & penable_rd;
assign  apb_rd_en = psel_rd & ~pwrite_rd;

三、地址映射

wire rg_err_flag_hp_wren = apb_wr_ps & (paddr_wr[(ADDR_DIDTH-1):0] == RG_ERR_FLAG_HP);
wire rg_err_flag_lp_wren = apb_wr_ps & (paddr_wr[(ADDR_DIDTH-1):0] == RG_ERR_FLAG_LP);

四、功能實現

 4.1、Clear條件的產生

//write 1 clear, input set
input wire [31:0]  hp_err_flag_set;
input wire [31:0]  lp_err_flag_set;

//write 1 clear
input wire [31:0]  hp_err_flag_clr;
input wire [31:0]  lp_err_flag_clr;  

assign hp_err_flag_clr = {32{rg_err_flag_hp_wren}} & pwdata[31:0];
assign lp_err_flag_clr = {32{rg_err_flag_lp_wren}} & pwdata[31:0];

 4.2、RTL實現

always @ (posedge clk or negedge rst_n) begin
  if(~rst_n)
    reg_err_hp_state <= 32'h0;
  else begin
    for(i = 0; i < 32; i = i + 1) begin
      reg_err_hp_state[i] <= hp_err_flag_state_set[i] ? 1'b1 :
                             hp_err_flag_state_clr[i] ? 1'b0 :
                             reg_err_hp_state[i] ;
    end
  end
end

always @ (posedge clk or negedge rst_n) begin
  if(~rst_n)
    reg_err_lp_state <= 32'h0;
  else begin
    for(i = 0; i < 32; i = i + 1) begin
      reg_err_lp_state[i] <= lp_err_flag_state_set[i] ? 1'b1 :
                             lp_err_flag_state_clr[i] ? 1'b0 :
                             reg_err_lp_state[i] ;
    end
  end
end

标签：wire,err,RTL,Register,rd,flag,類型,wr,apb
来源： https://blog.csdn.net/gsjthxy/article/details/105596197