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UVM RAL:Constructing Register Model 构建寄存器模型

作者:互联网

本节介绍如何构建用于寄存器和内存访问的 UVM 寄存器模型。

寄存器字段使用 uvm_reg_field 类型声明。

uvm_reg_field reg_name;

预定义的字段访问策略

Access Policy Description Effect of a Write on Current Field Value Effect of a Read on Current Field Value Read back Value
RO Read Only No effet No effet Current Value
RW Read, Write Changed to the written value No effet Current Value
RC Read Clears All No effet Sets all bits to 0’s Current Value
WRC Write, Read Clears All Changed to the written value Sets all bits to 0’s Current Value
WC Write Clears All Sets all bits to 0’s No effet Current Value
W1C Write 1 to Clear If the bit in the written value is a 1, the corresponding bit in the field is set to 0. Otherwise, the field bit is not affected No effet Current Value
W0C Write 0 to Clear If the bit in the written value is a 0, the corresponding bit in the field is set to 0. Otherwise, the field bit is not affected No effet Current Value

 

保留字段 Reserved Fields

 

Register

register 是通过编写一个从 uvm_reg 类扩展而来的类来构造的。每个唯一的寄存器类型必须有一个类

class my_reg extends uvm_reg;
  rand uvm_reg_field Field_0;
  rand uvm_reg_field Field_1;
endclass
class my_reg extends uvm_reg;
  virtual function build();
    this.Field_0 = my_reg::type_id::create(
      .name(“Field_0”),
      .parent(null),
      .contxt(get_full_name()));
    this.Field_0.configure(this, ...);
  endfunction
endclass

 

Register File

通过编写从 uvm_reg_file 类 扩展的类来构造 register file 类型

class my_reg_file extends uvm_reg_file;
  `uvm_object_utils(my_reg_file)
endclass

register file 类的名称在其声明范围内必须是唯一的

寄存器文件可以包含其他寄存器文件。

build() 方法应为所有register 和register 文件类属性调用 configure() 方法

class reg_file extends uvm_reg_file;
 
virtual function build();
  uvm_reg_block blk = get_block();
  this.rf = reg_file_0::type_id::create(
             .name($psprintf(“%s.rf1”, get_name())),
             .parent(null),
             .contxt(blk.get_full_name()));
  this.rf.configure(get_block(), this, ...);
  this.rf.build();
  this.rf.add_hdl_path();
endfunction
 
endclass

map() Method

//

//

//

virtual function map(uvm_reg_map mp, uvm_reg_addr_t offset);
  mp.add_reg(this.reg_0, base_addr + 'h0);
  mp.add_reg(this.reg_1, base_addr + 'h4;
  this.rf.map(mp, base_addr + 'h100);
endfunction

 

set_offset() Method

virtual function set_offset(uvm_reg_map mp, uvm_reg_addr_t offset);
  this.reg_0.set_offset(mp, base_addr + 'h0);
  this.reg_1.set_offset(mp, base_addr + 'h4);
  this.rf.set_offset(mp, base_addr + 'h100);
endfunction

 

Memory Types

 

class my_mem extends uvm_mem;
  `uvm_object_utils(my_mem)
endclass

 

 

Register Block

通过编写从 uvm_reg_block 类扩展的类来构造 block

block 类的名称在其声明范围内必须是唯一的

class my_blk extends uvm_reg_block;
  `uvm_object_utils(my_blk)
endclass

 block类型必须包含每个类的属性,

 这些应具有 rand 属性

 build() 方法应通过调用 uvm_reg_block::create_map() 方法来实例化所有命名的地址映射

 

标签:set,Constructing,RAL,Register,Value,uvm,offset,寄存器,reg
来源: https://www.cnblogs.com/fuqiangblog/p/16686497.html