HDLBits答案——Verilog Language
作者：互联网
Verilog Language
1 Basics
1.1 Wire
module top_module( input in, output out );
assign out = in;
endmodule
1.2 Wire4
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
1.3 Notgate
module top_module( input in, output out );
assign out =~in;
endmodule
1.4 Andgate
module top_module(
input a,
input b,
output out );
assign out = a&b;
endmodule
1.5 Norgate
module top_module(
input a,
input b,
output out );
assign out = ~(a|b);
endmodule
1.6 Xnorgate
module top_module(
input a,
input b,
output out );
assign out = ~((~a&b)|(a&~b));
endmodule
1.7 Declaring wires
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire e,f;
wire out_0;
assign e = a&b;
assign f = c&d;
assign out_0 = e|f;
assign out_n = ~out_0;
assign out = out_0;
endmodule
1.8 7458
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire a,b,c,d;
assign a = p1c&p1b&p1a;
assign b = p2a&p2b;
assign c = p2c&p2d;
assign d = p1f&p1e&p1d;
assign p2y = b|c;
assign p1y = a|d;
endmodule
2 Vector
2.1 Vector0
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0 ); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
endmodule
2.2 Vector1
`default_nettype none // Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
2.3 Vector2
module top_module(
input [31:0] in,
output [31:0] out );//
// assign out[31:24] = ...;
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
2.4 Vectorgates
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a|b;
assign out_or_logical = a||b;
assign out_not[5:3] = ~b;
assign out_not[2:0] = ~a;
endmodule
2.5 Gates4
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[3]&in[2]&in[1]&in[0];
assign out_or = in[3]|in[2]|in[1]|in[0];
assign out_xor = in[3]^in[2]^in[1]^in[0];
endmodule
2.6 Vector3
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
reg[1:0] t;
initial
begin
t = 2'b11;
end
// assign { ... } = { ... };
assign w[7:0] = {a[4:0],b[4:2]};
assign x[7:0] = {b[1:0],c[4:0],d[4]};
assign y[7:0] = {d[3:0],e[4:1]};
assign z[7:0] = {e[0],f[4:0],t};
endmodule
2.7 Vectorr
module top_module(
input [7:0] in,
output [7:0] out
);
assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
2.8 Vector4
module top_module (
input [7:0] in,
output [31:0] out );//
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}},in};
endmodule
2.9 Vector5
module top_module (
input a, b, c, d, e,
output [24:0] out );//
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out[24:20] = ~{5{a}}^{a,b,c,d,e};
assign out[19:15] = ~{5{b}}^{a,b,c,d,e};
assign out[14:10] = ~{5{c}}^{a,b,c,d,e};
assign out[9:5] = ~{5{d}}^{a,b,c,d,e};
assign out[4:0] = ~{5{e}}^{a,b,c,d,e};
endmodule
3 Modules:Hierarchy
3.1 Module
module top_module ( input a, input b, output out );
mod_a U1(a,b,out);
endmodule
3.2 Module pos
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a U1(out1,out2,a,b,c,d);
endmodule
3.3 Module name
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a U1(.out1(out1),.out2(out2),.in1(a),.in2(b),.in3(c),.in4(d));
endmodule
3.4 Module shift
module top_module ( input clk, input d, output q );
wire d1,d2;
my_dff U1(clk,d,d1);
my_dff U2(clk,d1,d2);
my_dff U3(clk,d2,q);
endmodule
3.5 Module shift8
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q0,q1,q2;
my_dff8 U0(clk,d,q0);
my_dff8 U1(clk,q0,q1);
my_dff8 U8(clk,q1,q2);
always @(sel)begin
case(sel)
2'b00:
q = d;
2'b01:
q = q0;
2'b10:
q = q1;
2'b11:
q = q2;
default:
q = 0;
endcase
end
endmodule
3.6 Module add
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout1;
add16 U1( a[15:0], b[15:0], 0, sum[15:0], cout1 );
add16 U2( a[31:16], b[31:16], cout1, sum[31:16], );
endmodule
3.6 Module fadd
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//
wire cout1;
add16 U1( a[15:0], b[15:0], 0, sum[15:0], cout1 );
add16 U2( a[31:16], b[31:16], cout1, sum[31:16], );
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
// Full adder module here
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule
3.7 Module cseladd
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout1;
wire [15:0] sum0,sum1,sum_l,sum_h;
add16 U1( a[15:0], b[15:0], 0, sum_l, cout1 );
add16 U2( a[31:16], b[31:16], 0,sum0, );
add16 U3( a[31:16], b[31:16], 1,sum1, );
always @(*)begin
if(cout1)
begin
sum_h = sum1;
end
else
begin
sum_h = sum0;
end
end
assign sum = {sum_h,sum_l};
endmodule
3.8 Module addsub
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout1;
wire [31:0] b1;
always @(*) begin
if(sub)
b1 = ~b;
else
b1 = b;
end
add16 U1( a[15:0], b1[15:0], sub, sum[15:0], cout1 );
add16 U2( a[31:16], b1[31:16], cout1, sum[31:16], );
endmodule
4 Procedures
4.1 Alwaysblock1
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a&b;
always @(*)begin
out_alwaysblock = a&b;
end
endmodule
4.2 Alwaysblock2
// synthesis verilog_input_version verilog_2001
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff );
assign out_assign = a^b;
always @(*)begin
out_always_comb = a^b;
end
always @(posedge clk)begin
out_always_ff = a^b;
end
endmodule
4.3 Always if
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
assign out_assign = (sel_b1&sel_b2)? b:a;
wire [1:0] sel;
assign sel = {sel_b1,sel_b2};
always @(*)begin
case(sel)
0:out_always = a;
1:out_always = a;
2:out_always = a;
3:out_always = b;
endcase
end
endmodule
4.4 Always if2
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else
shut_off_computer = 0;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else
keep_driving = 0;
end
endmodule
4.5 Always case
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
3'b000:out = data0;
3'b001:out = data1;
3'b010:out = data2;
3'b011:out = data3;
3'b100:out = data4;
3'b101:out = data5;
default:out = 0;
endcase
end
endmodule
4.6 Always case2
// synthesis verilog_input_version verilog_2001
module top_module (
input [3:0] in,
output reg [1:0] pos );
always @(*) begin
case(in)
4'b0000 : pos = 0;
4'b0001 : pos = 0;
4'b0010 : pos = 1;
4'b0011 : pos = 0;
4'b0100 : pos = 2;
4'b0101 : pos = 0;
4'b0110 : pos = 1;
4'b0111 : pos = 0;
4'b1000 : pos = 3;
4'b1001 : pos = 0;
4'b1010 : pos = 1;
4'b1011 : pos = 0;
4'b1100 : pos = 2;
4'b1101 : pos = 0;
4'b1110 : pos = 1;
4'b1111 : pos = 0;
endcase
end
endmodule
4.7 Always casez
// synthesis verilog_input_version verilog_2001
module top_module (
input [7:0] in,
output reg [2:0] pos );
always @(*)begin
casez(in)
8'bzzzzzzz1:pos=0;
8'bzzzzzz1z:pos=1;
8'bzzzzz1zz:pos=2;
8'bzzzz1zzz:pos=3;
8'bzzz1zzzz:pos=4;
8'bzz1zzzzz:pos=5;
8'bz1zzzzzz:pos=6;
8'b1zzzzzzz:pos=7;
default:pos=0;
endcase
end
endmodule
4.8 Always nolatches
// synthesis verilog_input_version verilog_2001
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up );
always @(*)begin
up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
case (scancode)
16'he06b:left = 1;
16'he072:down = 1;
16'he074:right = 1;
16'he075:up = 1;
default: ;
endcase
end
endmodule
5 More Verilog Features
5.1 Conditional
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
// assign intermediate_result1 = compare? true: false;
wire [7:0] min1,min2;
assign min1 =(a<b)? a: b;
assign min2 =(min1<c)? min1: c;
assign min =(min2<d)? min2: d;
endmodule
5.2 Reduction
module top_module (
input [7:0] in,
output parity);
assign parity = ^in[7:0];
endmodule
5.3 Gates100
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = &in[99:0];
assign out_or = |in[99:0];
assign out_xor = ^in[99:0];
endmodule
5.4 Vector100r
module top_module(
input [99:0] in,
output [99:0] out
);
integer i;
always @(*)begin
for(i = 0;i<100;i++)
out[i] = in[99-i];
end
endmodule
5.5 Popcount255
module top_module(
input [254:0] in,
output [7:0] out );
integer i;
always @(*)begin
out = 0;
for(i=0;i<255;i++)
if(in[i]==1) out++;
else out = out;
end
endmodule
5.6 Adder100i
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
integer i;
add8 L1(a[7:0],b[7:0],cin,sum[7:0],cout[7:0]);
add8 L2(a[15:8],b[15:8],cout[7],sum[15:8],cout[15:8]);
add8 L3(a[23:16],b[23:16],cout[15],sum[23:16],cout[23:16]);
add8 L4(a[31:24],b[31:24],cout[23],sum[31:24],cout[31:24]);
add8 L5(a[39:32],b[39:32],cout[31],sum[39:32],cout[39:32]);
add8 L6(a[47:40],b[47:40],cout[39],sum[47:40],cout[47:40]);
add8 L7(a[55:48],b[55:48],cout[47],sum[55:48],cout[55:48]);
add8 L8(a[63:56],b[63:56],cout[55],sum[63:56],cout[63:56]);
add8 L9(a[71:64],b[71:64],cout[63],sum[71:64],cout[71:64]);
add8 L10(a[79:72],b[79:72],cout[71],sum[79:72],cout[79:72]);
add8 L11(a[87:80],b[87:80],cout[79],sum[87:80],cout[87:80]);
add8 L12(a[95:88],b[95:88],cout[87],sum[95:88],cout[95:88]);
add1 P1(a[96],b[96],cout[95],sum[96],cout[96]);
add1 P2(a[97],b[97],cout[96],sum[97],cout[97]);
add1 P3(a[98],b[98],cout[97],sum[98],cout[98]);
add1 P4(a[99],b[99],cout[98],sum[99],cout[99]);
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
// Full adder module here
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule
module add8 ( input [7:0]a, input [7:0] b, input cin ,output [7:0] sum,output [7:0] cout);
add1 U1(a[0],b[0],cin,sum[0],cout[0]);
add1 U2(a[1],b[1],cout[0],sum[1],cout[1]);
add1 U3(a[2],b[2],cout[1],sum[2],cout[2]);
add1 U4(a[3],b[3],cout[2],sum[3],cout[3]);
add1 U5(a[4],b[4],cout[3],sum[4],cout[4]);
add1 U6(a[5],b[5],cout[4],sum[5],cout[5]);
add1 U7(a[6],b[6],cout[5],sum[6],cout[6]);
add1 U8(a[7],b[7],cout[6],sum[7],cout[7]);
endmodule
5.8 Bcdadd100
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire [399:0] cout_tmp;
bcd_fadd U1(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout_tmp[0]),.sum(sum[3:0]));
generate
genvar i;
for(i = 4; i < 400; i=i+4) begin : adder
bcd_fadd fadd(.a(a[i+3:i]), .b(b[i+3:i]), .cin(cout_tmp[i-4]), .cout(cout_tmp[i]),.sum(sum[i+3:i]));
end
endgenerate
assign cout = cout_tmp[396];
endmodule
标签：cout,Language,HDLBits,module,Verilog,output,input,assign,out 来源： https://www.cnblogs.com/hubuguilai/p/16592735.html