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日常记录(97)tcl与其它

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TCL 简介

tool command language,广泛用于EDA自动化的一种脚本语言。

设置变量

set a 1

1

set b $a+1

1+1

set c [expr $b+1]

3
当TCL解释器遇到字符[时,它就会把随后的expr作为一个命令名,从而激活与expr对应的过程。
expr 为计算字符串表达式得到的最终值

转义

TCL语言中的反斜杠置换类似于C语言中反斜杠的用法,主要用于在单词符号中插入诸如换行符、空格、[、$等被TCL解释器当作特殊符号对待的字符。

例子1

set c \I'am\ a\ big

I'am a big
反斜杠置换:
image

双引号和花括号

双引号除了中括号和美元符号,都被识别为正常字符

set d "I'am a big [expr 1+2]"

I'am a big 3
花括号用于变量中存在特殊的字符,把整体作为变量

set a ${b.1}

数组

更像是键值对的形式。括号为键,后面为值。

set day(s) 1
set day(x) 2

unset

删除变量

unset a

append

追加变量

append txt "aaa bbb"

txt的内容追加上一段字符串

incr

加法

incr a 3

a = a + 3的加法

list 列表

% list 1 {2 3 }
1 {2 3 }

concat

% concat {1 2 } {3 4}
1 2 3 4

lindex

% lindex {1 2 3 {4 5} } 1
2

% lindex {1 2 3 {4 5} } 1
2
% lindex {1 2 3 {4 5} } 4
% lindex {1 2 3 {4 5} } 3
4 5

llength

% llength {1 2 3 {4 5} }
4

linsert

% linsert {1 2 3 {4 5} } 4 {2 3}
1 2 3 {4 5} {2 3}

lappend

% lappend {1 2 3} {3 3 4}
{3 3 4}
% echo $a
7
% lappend a {3 4 5}
7 {3 4 5}
% echo $a
7 {3 4 5}

if 语句

set a 1
if {$a==1} {
    set a 2
} elseif { $a==2 } {
    set a 3
} else {
    set a 100
}
puts [format "value a in if is %d" $a]

while语句

set i 10
set cnt 0
while {$i>=0} {
    incr i -1
    set cnt [expr $cnt+2]
}
puts [format "value cnt in while is %d" $cnt]

for 语句

set e 0
for {set var 0} {$var < 10} {incr var} {
    incr e 2
}
puts [format "value e in for is %d" $e]

foreach语句

set bb 0
foreach aa {1 2 3} {
    incr bb
}
puts [format "value bb in foreach is %d" $bb]

switch 语句

set var "aaccdd"
set cc 20
switch $var {
    aaccdd {
        set cc 10
    }
    default {
        set cc 0
    }
}
puts [format "value c in for is %d" $c]

exec命令

eval set a 1; set b 2
set date_msg [exec date]
puts $date_msg

proc过程

set a 100
set d 0
proc add {x y} {
    global a
    global d
    set d [expr $x+$y+$a]
    return $d
}
set c [add 2 3]

format命令

puts [format "value ccc in for is %d" $cc]

scan命令

第一个参数是原始数据,第二个参数是扫描数据,然后a和b被填值

set a 1
set b 2
set scan_msg [scan "some 26 32" "some %d %d" a b]
puts [format "value a is %0d value b is %0d" $a $b]

输出结果

value a in if is 2
value cnt in while is 22
value e in for is 20
value bb in foreach is 3
value ccc in for is 10
Mon 20 Jun 10:40:32 CST 2022
value c in for is 105
value a is 26 value b is 32

sv

动态数组

需要new,然后才能使用,否则放不进数据。
队列不用new。

module taa ();
    int a[] = {1,2,3,4,5};
    int b[];
    int c[$];
    initial begin
        /* b = new[10]; */
        b[0] = 1;
        b[1] = 2;
        $display("a is %p", a);
        $display("b is %p", b);
        c.push_back(4);
        c.push_back(5);
        c.push_back(6);
        $display("c is %p", c);
    end
endmodule

输出结果:

a is '{1, 2, 3, 4, 5}
b is '{}
c is '{4, 5, 6}

iff

可以在时钟上使用iff判断

module taa ();
    logic clk, rstn;

    initial begin
        #5 ;
        @(posedge clk iff rstn == 1);
        $display("time is %0d", $time);
    end

    initial begin
        clk = 0;
        forever begin
            #10 clk = ~clk;
        end
    end

    initial begin
        rstn = 0;
        #50 rstn = 1;
        #100;
        $finish();
    end
endmodule

输出

Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jun 20 12:34 2022
time is 50
$finish called from file "taa.sv", line 21.

local在外部约束

local是当前的,然后得到是当前的外部值。

module taa ();
    class local_test;
        rand int a;
        constraint cons1{
            soft a == 1;
        }
    endclass: local_test

    initial begin
        int a = 2;
        local_test lt = new();
        local_test lt2 = new();
        local_test lt3 = new();

        lt.randomize with {a == a;};
        $display("1. value a is %0d", lt.a);
        lt2.randomize with {a == local::a;};
        $display("2. value a is %0d", lt2.a);
        lt3.randomize;
        $display("3. value a is %0d", lt3.a);

    end
endmodule

输出

1. value a is 1
2. value a is 2
3. value a is 1

uvm_resource_db

uvm_resource_db虽然是确实缺少了层次信息,但是从测试结果上看,仍然是top-down的,而非是就近原则的赋值

module taa ();
    import uvm_pkg::*;

    class agent_base extends uvm_agent;
        `uvm_component_utils(agent_base)
        int a;
        int b;

        function new(string name="agent_base", uvm_component parent);
            super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
            super.build_phase(phase);
            uvm_config_db#(int)::get(this, "", "value_a", a);
            uvm_resource_db#(int)::read_by_name("env_name11", "value_b", b);
        endfunction: build_phase

        function void start_of_simulation_phase(uvm_phase phase);
            `uvm_info("VALUE_A", $sformatf("value a is %0d", a), UVM_LOW)
            `uvm_info("VALUE_B", $sformatf("value b is %0d", b), UVM_LOW)
            uvm_top.print_topology();
        endfunction:start_of_simulation_phase
    endclass: agent_base

    class base_env extends uvm_env;
        `uvm_component_utils(base_env)
        agent_base agt;

        function new(string name="base_env", uvm_component parent);
            super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
            agt = agent_base::type_id::create("agent_name", this);
            uvm_config_db#(int)::set(this, "agent_name", "value_a", 20);
            uvm_resource_db#(int)::set("env_name11", "value_b", 50);
            `uvm_info("PRINT_LOG", $sformatf("base env ok"), UVM_LOW)
        endfunction:build_phase

    endclass: base_env

    class test_base extends uvm_test;
        `uvm_component_utils(test_base)
        base_env env;

        function new(string name="test_base", uvm_component parent);
            super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
            super.build_phase(phase);
            env = base_env::type_id::create("env_name", this);
            uvm_config_db#(int)::set(this, "env_name.agent_name", "value_a", 10);
            uvm_resource_db#(int)::set("env_name11", "value_b", 30);
            `uvm_info("PRINT_LOG", $sformatf("test_base ok"), UVM_LOW)
        endfunction: build_phase
    endclass: test_base

    initial begin
        run_test("test_base");
    end
endmodule

输出

UVM_INFO @ 0: reporter [RNTST] Running test test_base...
UVM_INFO taa.sv(56) @ 0: uvm_test_top [PRINT_LOG] test_base ok
UVM_INFO taa.sv(38) @ 0: uvm_test_top.env_name [PRINT_LOG] base env ok
UVM_INFO taa.sv(20) @ 0: uvm_test_top.env_name.agent_name [VALUE_A] value a is 10
UVM_INFO taa.sv(21) @ 0: uvm_test_top.env_name.agent_name [VALUE_B] value b is 30
UVM_INFO /home/synopsys/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(589) @ 0: reporter [UVMTOP] UVM testbench topology:
---------------------------------------
Name            Type        Size  Value
---------------------------------------
uvm_test_top    test_base   -     @335
  env_name      base_env    -     @348
    agent_name  agent_base  -     @365
---------------------------------------

标签:set,value,tcl,base,日常,env,test,97,uvm
来源: https://www.cnblogs.com/bai2022/p/16391622.html