Fsm serialdata

现在您有了一个有限状态机，可以识别何时在串行比特流中正确接收到字节，添加一个数据路径来输出正确接收到的数据字节。 out_byte 需要在 done 为 1 ，否则不在乎。

请注意，串行协议首先发送 最低 有效位。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
localparam  IDLE=0,START=1,DATA=2,STOP=3,ERROR=4;
    reg [2:0] state,nstate;
    reg [3:0] cnt;
    reg [7:0] out;
always@(posedge clk)
    if(reset)
            state<=IDLE;
    else
        state<=nstate;

    always@(posedge clk)
        if(reset)
            cnt<=4'd0;
    else
        case(nstate)
            START:cnt<=4'd0;
            DATA:cnt<=cnt+4'd1;
            default:cnt<=cnt;
        endcase
    always@(*)
        begin
            case(state)
                IDLE:nstate=in?IDLE:START;
                START:nstate=DATA;
                DATA:nstate=(cnt==4'd8)?(in?STOP:ERROR):DATA;
                STOP:nstate=in?IDLE:START;
                ERROR:nstate=in?IDLE:ERROR;
                default:nstate=IDLE;
            endcase
        end
    
    always@(posedge clk)begin
    if(reset)
        out<=8'b0;
        else
            out<={in,out[7:1]};   
    end
    always@(posedge clk)
        if(reset)
            out_byte<=8'd0;
    else if(nstate==STOP)
        out_byte<=out;
    else
        out_byte<=out_byte;
    assign done=(state==STOP);
endmodule

标签：reset,cnt,nstate,STOP,Fsm,IDLE,serialdata,out
来源： https://www.cnblogs.com/usst6/p/16317055.html