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led的进化

作者:互联网

 

module led_change1(      //1.一个led亮100ns,灭400ns,循环
    clk,
    reset,
    led
    );
    input clk;
    input reset;
    output reg led = 1'd1;
    reg [4:0]counter0;
    

    
    always@( posedge clk or negedge reset )
    begin       
    if ( reset == 0 )
    counter0 <= 5'b0 ;
    else if (counter0 == 24 )
    counter0 <= 0 ;
    else 
    counter0 <= counter0 + 1'd1;  
    end 
    
    always@( posedge clk or negedge reset ) 
    begin
    if ( reset == 0 )
    led <= 0 ;
    else if (counter0 == 4 )
    led <= ! led ;
    else if (counter0 == 24 )
    led <= ! led ;
    else 
    led <= led;//记得
    end    
    
endmodule
module led_change2(      //2.一个led亮2500ns,灭5000ns,亮7500ns,灭10000ns循环
    clk,
    reset,
    led
    );
    input clk;
    input reset;
    output reg led = 1'd1;
    reg [11:0]counter0;
    
    parameter  mcnt = 1250 ;
    
    always@( posedge clk or negedge reset )
    begin       
    if ( reset == 0 )
    counter0 <= 5'b0 ;
    else if (counter0 == mcnt - 1 )
    counter0 <= 0 ;
    else 
    counter0 <= counter0 + 1'd1;  
    end 
    
//    always@( posedge clk or negedge reset ) 
//    begin
//    if ( reset == 0 )
//    led <= 0 ;
//    else if (counter0 == mcnt * 1 / 10 - 1 )
//    led <= ! led ;
//    else if (counter0 == mcnt * 3 / 10 - 1 )
//    led <= ! led ;
//    else if (counter0 == mcnt * 6 / 10 - 1 )
//    led <= ! led ;
//    else if (counter0 == mcnt * 10 / 10 - 1 )
//    led <= ! led ;
//    else 
//    led <= led;//记得
//    end    
    
 always@( posedge clk or negedge reset ) 
    begin
        if ( reset == 0 )
        led <= 0 ;
        else case( counter0 ) 
        mcnt * 1 / 10 - 1 : led <= ! led ;
        mcnt * 3 / 10 - 1 : led <= ! led ;
        mcnt * 6 / 10 - 1 : led <= ! led ;
        mcnt * 10 / 10 - 1 : led <= ! led ;
        endcase
    end    
endmodule
module led_change3(      //3.以2500ns为变化周期,20000ns为一个循环,每个周期的亮灭模式由用户设置。
    clk,
    reset,
    ctrl,
    led
    );
    input clk;
    input reset;
    input [7:0]ctrl;
    output reg led ;
    
    reg [9:0]counter0;
    
    parameter  mcnt = 1000 ;
    
    always@( posedge clk or negedge reset )
    begin       
        if ( reset == 0 )
        counter0 <= 11'b0 ;
        else if (counter0 == mcnt - 1 )
        counter0 <= 0 ;
        else 
        counter0 <= counter0 + 1'd1;  
    end 
     
    always@( posedge clk or negedge reset ) 
    begin
        if ( reset == 0 )
        led <= 0 ;
        else case( counter0 ) 
        mcnt * 1 / 8 - 1 : led <= ctrl[0] ;
        mcnt * 2 / 8 - 1 : led <= ctrl[1] ;
        mcnt * 3 / 8 - 1 : led <= ctrl[2] ;
        mcnt * 4 / 8 - 1 : led <= ctrl[3] ;
        mcnt * 5 / 8 - 1 : led <= ctrl[4] ;
        mcnt * 6 / 8 - 1 : led <= ctrl[5] ;
        mcnt * 7 / 8 - 1 : led <= ctrl[6] ;
        mcnt * 8 / 8 - 1 : led <= ctrl[7] ;
        default led <= led ;
        endcase
    end    
endmodule
module led_change4(      //4.以tim*20/8 ns为变化周期,tim*20 ns为一个循环,每个周期的亮灭模式,tim由用户设置。.
    clk,
    reset,
    ctrl,
    tim,
    led
    );
    input clk;
    input reset;
    input [7:0]ctrl;
    input [9:0]tim;
    output reg led ;
    
    reg [9:0]counter0;
    
    always@( posedge clk or negedge reset )
    begin       
        if ( reset == 0 )
        counter0 <= 11'b0 ;
        else if (counter0 == tim - 1 )
        counter0 <= 0 ;
        else 
        counter0 <= counter0 + 1'd1;  
    end 
     
    always@( posedge clk or negedge reset ) 
    begin
        if ( reset == 0 )
        led <= 0 ;
        else case( counter0 )                   //可以用第二个计数器的方法来设置判断条件
        tim * 1 / 8 - 1 : led <= ctrl[0] ;
        tim * 2 / 8 - 1 : led <= ctrl[1] ;
        tim * 3 / 8 - 1 : led <= ctrl[2] ;
        tim * 4 / 8 - 1 : led <= ctrl[3] ;
        tim * 5 / 8 - 1 : led <= ctrl[4] ;
        tim * 6 / 8 - 1 : led <= ctrl[5] ;
        tim * 7 / 8 - 1 : led <= ctrl[6] ;
        tim * 8 / 8 - 1 : led <= ctrl[7] ;
        default led <= led ;
        endcase
    end    
endmodule
module led_change4(      //5.1以tim*20/8 ns为变化周期,tim*20 ns为一个循环,每个周期的亮灭模式,tim由用户设置。.
    clk,
    reset,
    ctrl,
    tim,
    led
    );
    input clk;
    input reset;
    input [7:0]ctrl;
    input [9:0]tim;
    output reg led ;
    
    reg [9:0]counter0;
    
    always@( posedge clk or negedge reset )
    begin       
        if ( reset == 0 )
        counter0 <= 11'b0 ;
        else if (counter0 == tim - 1 )
        counter0 <= 0 ;
        else 
        counter0 <= counter0 + 1'd1;  
    end 
     
    always@( posedge clk or negedge reset ) 
    begin
        if ( reset == 0 )
        led <= 0 ;
        else case( counter0 )                   //可以用第二个计数器的方法来设置判断条件
        tim * 1 / 8 - 1 : led <= ctrl[0] ;
        tim * 2 / 8 - 1 : led <= ctrl[1] ;
        tim * 3 / 8 - 1 : led <= ctrl[2] ;
        tim * 4 / 8 - 1 : led <= ctrl[3] ;
        tim * 5 / 8 - 1 : led <= ctrl[4] ;
        tim * 6 / 8 - 1 : led <= ctrl[5] ;
        tim * 7 / 8 - 1 : led <= ctrl[6] ;
        tim * 8 / 8 - 1 : led <= ctrl[7] ;
        default led <= led ;
        endcase
    end    
endmodule
module led_change5_M(      //5.2最小周期相同(由用户指定),由多个ctrl控制多个led在其周期内循环亮灭,用例化模块的方法
    clk,
    reset,
    ctrlA,
    ctrlB,
    tim,
    led    
    );
    input clk;
    input reset;
    input [7:0]ctrlA,ctrlB;
    input [9:0]tim;
    output wire [1:0]led ;
    
    led_change4 led_change4_sim0(      //以tim*20/8 ns为变化周期,tim*20 ns为一个循环,每个周期的亮灭模式,tim由用户设置。
    .clk(clk),
    .reset(reset),
    .ctrl(ctrlA),
    .tim(tim),
    .led(led[0])
    );
    
    led_change4 led_change4_sim1(      //以tim*20/8 ns为变化周期,tim*20 ns为一个循环,每个周期的亮灭模式,tim由用户设置。
    .clk(clk),
    .reset(reset),
    .ctrl(ctrlB),
    .tim(tim),
    .led(led[1])
    );

endmodule
module led_change6(      //6.每隔Tim秒,led的一个8状态周期tim循环一次,Tim>tim,两个参数都由用户设置。
    clk,
    reset,
    ctrl,
    tim,
    Tim,
    led
    );
    input clk;
    input reset;
    input [7:0]ctrl;
    input [9:0]tim;
    input [10:0]Tim;
    output reg led ;
    
    reg [10:0] counter0;
    
    always@( posedge clk or negedge reset )
    begin       
        if ( reset == 0 )
        counter0 <= 9'b0 ;
        else if (counter0 == Tim -1  )
        counter0 <= 0 ;
        else 
        counter0 <= counter0 + 1'd1;  
    end 
     
    always@( posedge clk or negedge reset ) 
    begin
        if ( reset == 0 )
        led <= 0 ;
        else case( counter0 )                   //可以用第二个计数器的方法来设置判断条件
        tim * 1 / 8 - 1 : led <= ctrl[0] ;
        tim * 2 / 8 - 1 : led <= ctrl[1] ;
        tim * 3 / 8 - 1 : led <= ctrl[2] ;
        tim * 4 / 8 - 1 : led <= ctrl[3] ;
        tim * 5 / 8 - 1 : led <= ctrl[4] ;
        tim * 6 / 8 - 1 : led <= ctrl[5] ;
        tim * 7 / 8 - 1 : led <= ctrl[6] ;
        tim * 8 / 8 - 1 : led <= ctrl[7] ;
        tim * 9 / 8 - 1 : led <= 0 ;
        default led <= led ;
        endcase
    end    
endmodule

 注意:

1.需要用户指定的便需要设置输入端口,这是一个变量。

2.用if语句时可以用else 罗列其他没有写出的情况。而用case语句时应该用default xxxxx。语句实现,见上面3和4。同时,可以用if先列出复位信号的情况,再用else case罗列时钟信号的情况。

3.工程包含多个文件时,用set as top来激活指定要操作的文件。

4.乘除可以使用左右移位来实现,节省乘法器。

5.用顶层中例化模块的方法十分便捷有效,只需要把顶层的引脚分别分配给多个例化模块就可以了。要学会这么用,很快很好用。

6.多位宽既可以用来表示多个输出端口,也可以用来表示一个端口的不同时期的多个状态。

7.参数赋值时,要明确指定进制,不然会默认是十进制,有时候不注意就会出错。养成良好习惯。

8.错误:counter设定位宽太小,导致计数不到第二个else if就已经溢出,成为0,波形一直在重复前面的结果,后面的结果没有出现,难以看出错误。所以遇到我们设置的有些预期结果没有出现的情况,要检查一下计时器的位宽设置有没有出错。因为溢出不报错,但影响结果。

9.记住:仿真设置的例化module参数的位宽必须与原来module的参数位宽保持一致,不然虽然没有报错,但是输出会出错。

10.再次记忆:顶层设计时的输出端写为wire,底层是reg。顶层写reg会报错。

 

标签:reset,led,进化,clk,tim,input,reg
来源: https://www.cnblogs.com/fbur/p/16273296.html