1.简介

(1) uvm cmdline processor是用来处理命令行信息的单实例类,便于将任意数量的参数传递到uvm环境中;

(2) uvm_cmdline processor有助于通过传递参数控制仿真以及debug uvm环境;

 1 const uvm_cmdline_processor uvm_cmdline_proc = uvm_cmdline_processor::get_inst();
 2 
 3 class uvm_cmdline_processor extends uvm_report_object;
 4 
 5   static local uvm_cmdline_processor m_inst;
 6 
 7   // Group: Singleton 
 8 
 9   // Function: get_inst
10   //
11   // Returns the singleton instance of the UVM command line processor.
12 
13   static function uvm_cmdline_processor get_inst();
14     if(m_inst == null) 
15       m_inst = new("uvm_cmdline_proc");
16     return m_inst;
17   endfunction
18   ...
19 endclass

2.available global settings

(1)+UVM_DUMP_CMDLINE_ARGS: 用于dump所有的命令行参数;

(2)+UVM_TESTNAME:+UVM_TESTNAME=<class name>~允许user指明哪个uvm_test或uvm_component会通过factory机制被实例化;

1 <sim command> +UVM_TESTNAME=read_modify_write_test

(3)+UVM_VERBOSITY:+UVM_VERBOSITY=<verbosity>允许user指明所有uvm组件的初始冗余度阈值;

1 <sim command> +UVM_VERBOSITY=UVM_HIGH

(4)+UVM_TIMEOUT:+UVM_TIMEOUT=<timeout>,<overridable>允许user指明global timeout时间;

1 <sim command> +UVM_TIMEOUT=200000,NO

(5)+UVM_MAX_QUIT_COUNT:+UVM_MAX_QUIT_COUNT=<count>,<overridable>允许user设置UVM_EXIT action执行前,所能容忍的count action的最大数量;

1 <sim command> +UVM_MAX_QUIT_COUNT=5,NO

(6)+UVM_PHASE_TRACE:使能phase执行的追踪;

1 +UVM_PHASE_TRACE

(7)+UVM_OBJECTION_TRACE:使能objection的追踪;

1 +UVM_OBJECTION_TRACE

(8)+UVM_RESOURCE_DB_TRACE:使能resource_db访问的追踪;

1 +UVM_RESOURCE_DB_TRACE

(9)+UVM_CONFIG_DB_TRACE:使能config_db访问的追踪;

1 +UVM_CONFIG_DB_TRACE

3.控制仿真行为的命令行参数设置(与冗余度相关的,与严重性相关的,与配置相关的,与启动seq相关的,与重载相关的)

(1) +uvm_set_verbosity:+uvm_set_severity=<comp>,<id>,<current severity>,<new severity>用于重载冗余度;

1 <sim command> +uvm_set_severity=uvm_test_top.env0.*,BAD_CRC,UVM_ERROR,UVM_WARNING

(2) +uvm_set_action: +uvm_set_action=<comp>,<id>,<severity>,<action>用于设置指定组件指定id指定严重性级别信息对应的行为;

1 <sim command> +uvm_set_action=uvm_test_top.env0.*,_ALL_,UVM_ERROR,UVM_NO_ACTION

(3) +uvm_set_severity: +uvm_set_severity=<comp>,<id>,<current severity>,<new severity>用于重载指定组件指定id打印信息的严重性级别;

1 <sim command> +uvm_set_severity=uvm_test_top.env0.*,BAD_CRC,UVM_ERROR,UVM_WARNING

(4) +uvm_set_config_int:为指定组件的整型变量设置值;

1  <sim command> +uvm_set_config_int=uvm_test_top.soc_env,mode,5

(5) +uvm_set_config_string:为指定组件的字符串类型变量设置值;

(6) +uvm_set_default_sequence:+uvm_set_default_sequence=<seqr>,<phase>,<type>设置default sequence;

1 <sim command> +uvm_set_default_sequence=path.to.sequencer,main_phase,seq_type

(7) +uvm_set_inst_override & +uvm_set_type_override

1 +uvm_set_inst_override=<req_type>,<override_type>,<full_inst_path>
2 +uvm_set_type_override=<req_type>,<override_type>[,<replace>]

4.debug switches

(1)+UVM_PHASE_TRACE

(2)+UVM_OBJECTION_TRACE

(3)+UVM_RESOURCE_DB_TRACE

(4)+UVM_CONFIG_DB_TRACE

5.uvm_cmdline_processor常用函数及示例

 1 class A extends uvm_component;
 2     ...
 3     int slave_adr_max;
 4     ...
 5     function new(string name, uvm_component parent);
 6         super.new(name, parent);
 7     endfunction
 8 
 9     virtual function void build_phase(uvm_phase phase);
10         uvm_cmdline_processor clp;
11         string arg_values[$];
12         clp=uvm_cmdline_processor::get_inst();
13         void'(clp.get_arg_values("+slave_adr_max=", arg_values));
14         slave_adr_max=arg_values[0].atoi();
15         `uvm_info("CMDLINE_VALUE",$sformatf("slave_adr_max=%h",slave_adr_max),UVM_LOW)
16     endfunction
17 endclass

 

标签：set,TRACE,cmdline,UVM,processor,uvm
来源： https://www.cnblogs.com/csjt/p/16256182.html