注1:uvm lab1 - __见贤思齐 - 博客园 (cnblogs.com)

1.test.sv

(1)和uvm lab1中test.sv相同;

2.test_collection.sv

 1 `ifndef TEST_COLLECTION__SV
 2 `define TEST_COLLECTION__SV
 3 
 4 `include "router_env.sv"
 5 
 6 class test_base extends uvm_test;
 7   `uvm_component_utils(test_base)
 8   router_env env;
 9 
10   function new(string name, uvm_component parent);
11     super.new(name, parent);
12     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
13   endfunction
14 
15   virtual function void build_phase(uvm_phase phase);
16     super.build_phase(phase);
17     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
18     env = router_env::type_id::create("env", this);
19   endfunction
20 
21 //
22 // The start_of_simulation_phase method from lab1 is moved to final_phase
23 // for the convinience of seeing the topology and factory registry at the
24 // end of simulation.  In practice, you should implement both phases to
25 // display the topology and the factory registry.
26 //
27   virtual function void final_phase(uvm_phase phase);
28     super.final_phase(phase);
29     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
30     uvm_top.print_topology();
31     factory.print();
32   endfunction
33 endclass
34 
35 // Lab 2 - Include the packet_da_3.sv file
36 //
37 // ToDo
38 `include "packet_da_3.sv"
39 
40 
41 class test_da_3_inst extends test_base;
42   `uvm_component_utils(test_da_3_inst)
43 
44   function new(string name, uvm_component parent);
45     super.new(name, parent);
46     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
47   endfunction
48 
49   virtual function void build_phase(uvm_phase phase);
50     super.build_phase(phase);
51     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
52 
53     // Lab 2 - Use instance override to configure the packet sequencer
54     //         to use packet_da_3 instead of packet
55     //
56     // ToDo
57     set_inst_override_by_type("env.i_agent*.seqr.*", packet::get_type(), packet_da_3::get_type());
58 
59 
60   endfunction
61 
62 endclass
63 
64 // Optional Lab 2 - Create a test to globally set all packet instances to packet_da_3
65 
66 class test_da_3_type extends test_base;
67   `uvm_component_utils(test_da_3_type)
68 
69   function new(string name, uvm_component parent);
70     super.new(name, parent);
71     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
72   endfunction
73 
74   virtual function void build_phase(uvm_phase phase);
75     super.build_phase(phase);
76     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
77     set_type_override_by_type(packet::get_type(), packet_da_3::get_type());
78   endfunction
79 endclass
80 
81 
82 `endif

3.router_env.sv

(1)和uvm lab1中router_env.sv相同;

4.input_agent.sv

(1)和uvm lab1中input_agent.sv相同;

5.driver.sv

(1)和uvm lab1中driver.sv相同;

6.packet_sequence.sv

(1)和uvm lab1中packet_sequence.sv相同;

7.packet.sv

(1)和uvm lab1中packet.sv相同;

8.packet_da_3.sv

 1 `ifndef PACKET_DA_3__SV
 2 `define PACKET_DA_3__SV
 3 
 4 class packet_da_3 extends packet;
 5   `uvm_object_utils(packet_da_3)
 6 
 7   // Lab 2 - set the constraint for destination address (da) to 3
 8   //
 9   // ToDo
10   constraint da_3 {
11     da == 3;
12   }
13 
14   function new(string name = "packet_da_3");
15     super.new(name);
16    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
17   endfunction
18 endclass
19 
20 `endif

 

标签：sv,packet,da,lab2,test,uvm,phase
来源： https://www.cnblogs.com/csjt/p/16209815.html