HDLBITS————Verilog language——More verilog features

1. reduction operators
这儿是算校验位（第8位），如果8位in已经是偶数个1了，则补0，如果是奇数个，则补1；用单目异或缩位运算，11得0

module top_module (
    input [7:0] in,
    output parity); 
    
    assign parity = ^in;

endmodule

2. Popcount255
找位是1的个数，for之前可初始化值

module top_module( 
    input [254:0] in,
    output [7:0] out );
    
    integer i;
    always@(*)begin
        out = 0;
        for(i=0;i<255;i=i+1)begin
            out = out + in[i];
        end
    end
    
endmodule

3. 100bit adder
这部分来熟悉generate用法，它是在物理上放了那么多个例化模块

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    generate
        genvar i;
        for(i=0;i<100;i=i+1)begin:loop
            if(i==0)begin	//第一个
        		full_adder inst( 
                    .a(a[i]), 
                    .b(b[i]), 
            	    .cin(cin),
                    .cout(cout[i]), 
                    .sum(sum[i])
       	    	);
            end
            else begin
        		full_adder inst( 
                    .a(a[i]), 
                    .b(b[i]), 
                    .cin(cout[i-1]),
                    .cout(cout[i]), 
                    .sum(sum[i])
       	    	);                
            end
        end
    endgenerate
    
endmodule

module full_adder( 
    input a, b, cin,
    output cout, sum );
	
    assign {cout,sum} = a + b + cin;
        
endmodule

4. bcd_add100

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    
    wire [99:0]link_cout;
    
    generate
        genvar i;
        for(i=0;i<100;i=i+1)begin:loop
            if(i==0)begin	//第一个
        		bcd_fadd  inst( 
                    .a(a[4*i+3:i]), 
                    .b(b[4*i+3:i]), 
            	    .cin(cin),
                    .cout(link_cout[i]), 
                    .sum(sum[4*i+3:4*i])
       	    	);
            end
            else begin
        		bcd_fadd  inst( 
                    .a(a[4*i+3:4*i]), 
                    .b(b[4*i+3:4*i]), 
                    .cin(link_cout[i-1]),
                    .cout(link_cout[i]), 
                    .sum(sum[4*i+3:4*i])
       	    	);                
            end
        end
    endgenerate  
	
    assign cout = link_cout[99];
    
endmodule

标签：features,language,top,module,99,Verilog,output,input,generate
来源： https://blog.csdn.net/qq_41793792/article/details/123097070