阶段2-计数器练习15

 

 还是需两个计数器，一个变量Z，计数器加1条件改为 dout !=0，这样可以省点资源

 1 module cnt_test(
 2                 clk,
 3                 rst_n,
 4                 en1,
 5 //                en2,
 6 //                en3,
 7                 dout
 8 );
 9 
10 input     clk;
11 input     rst_n;
12 input      en1;
13 //input      en2;
14 //input      en3;
15 
16 output [2:0] dout;
17 
18 reg [2:0]    dout;
19 //reg         flag_add;
20 
21 reg [3:0] cnt0;
22 reg [3:0] cnt1;
23 //reg [3:0] x;
24 //reg [3:0] y;
25 reg [3:0] z;
26 //reg [3:0] flag_sel;
27  
28 wire add_cnt0;
29 wire end_cnt0;
30 
31 wire add_cnt1;
32 wire end_cnt1;
33 
34 always @(posedge clk or negedge rst_n)begin
35     if(!rst_n)begin
36         cnt0 <= 0;
37     end
38     else if(add_cnt0)begin
39         if(end_cnt0)begin
40             cnt0 <= 0;
41         end
42         else begin
43             cnt0 <= cnt0 + 1;
44         end
45     end
46 end
47 
48 assign add_cnt0 = (dout != 0); //计数器条件，直接使用dout != 0;
49 assign end_cnt0 = add_cnt0 && cnt0 == 5 - 1; 
50 
51 always @(posedge clk or negedge rst_n)begin
52     if(!rst_n)begin
53         cnt1 <= 0;
54     end
55     else if(add_cnt1)begin
56         if(end_cnt1)begin
57             cnt1 <= 0;
58         end
59         else begin
60             cnt1 <= cnt1 + 1;
61         end
62     end
63 end
64 
65 assign add_cnt1 = end_cnt0;
66 assign end_cnt1 = add_cnt1 && cnt1 == 3 - 1; 
67 
68 always @(posedge clk or negedge rst_n)begin
69     if(!rst_n)begin
70         dout <= 0;
71     end
72     else if(en1)begin
73         dout <= z;
74     end
75     else if(end_cnt0)begin
76         dout <= 0;
77     end
78 end
79 
80 always @(*)begin
81     if(cnt1 == 0)begin
82         z = 1;
83     end
84     else if(cnt1 == 1)begin
85         z = 2;
86     end
87     else begin //省去if(cnt1 == 2) 
88         z = 3;
89     end
90 end
91 
92 endmodule

测试文件：

 1 module top_sim();
 2 
 3 reg clk;
 4 reg rst_n;
 5 reg en1;
 6 //reg en2;
 7 //reg en3;
 8 wire dout;
 9 
10 parameter CLK_CYCLE    = 20;
11 
12 initial begin
13     clk = 0;
14     forever begin
15         #(CLK_CYCLE/2);
16         clk = ~clk;
17     end
18         
19 end
20 
21 initial begin
22     #1;
23     rst_n = 0;
24     #(CLK_CYCLE*2);
25     rst_n = 1;
26 end
27 
28 initial begin
29     #1;
30     en1 = 0;
31 //    en2 = 0;
32 //    en3 = 0;
33     repeat(20)begin
34         #(10*CLK_CYCLE);
35         en1 = 1;
36         #(1*CLK_CYCLE);
37         en1 = 0;
38         #(10*CLK_CYCLE);
39         en1 = 1;
40         #(1*CLK_CYCLE);
41         en1 = 0;
42         #(10*CLK_CYCLE);
43         en1 = 1;
44         #(1*CLK_CYCLE);
45         en1 = 0;
46     end
47 end
48 
49 
50 cnt_test        u1(    
51                         .clk(clk),
52                         .rst_n(rst_n),
53                         .en1(en1),
54 //                        .en2(en2),
55 //                        .en3(en3),
56                         .dout(dout)
57                         
58 );
59 
60 endmodule 

View Code

仿真波形：

 

 还是利用之前的flag_add条件来计数：

  1 module cnt_test(
  2                 clk,
  3                 rst_n,
  4                 en1,
  5 //                en2,
  6 //                en3,
  7                 dout
  8 );
  9 
 10 input     clk;
 11 input     rst_n;
 12 input      en1;
 13 //input      en2;
 14 //input      en3;
 15 
 16 output [2:0] dout;
 17 
 18 reg [2:0]    dout;
 19 reg         flag_add;
 20 
 21 reg [3:0] cnt0;
 22 reg [3:0] cnt1;
 23 //reg [3:0] x;
 24 //reg [3:0] y;
 25 reg [3:0] z;
 26 //reg [3:0] flag_sel;
 27  
 28 wire add_cnt0;
 29 wire end_cnt0;
 30 
 31 wire add_cnt1;
 32 wire end_cnt1;
 33 
 34 always @(posedge clk or negedge rst_n)begin
 35     if(!rst_n)begin
 36         cnt0 <= 0;
 37     end
 38     else if(add_cnt0)begin
 39         if(end_cnt0)begin
 40             cnt0 <= 0;
 41         end
 42         else begin
 43             cnt0 <= cnt0 + 1;
 44         end
 45     end
 46 end
 47 
 48 assign add_cnt0 = flag_add; //引入一个信号flag_add
 49 assign end_cnt0 = add_cnt0 && cnt0 == 5 - 1; 
 50 
 51 always @(posedge clk or negedge rst_n)begin
 52     if(!rst_n)begin
 53         cnt1 <= 0;
 54     end
 55     else if(add_cnt1)begin
 56         if(end_cnt1)begin
 57             cnt1 <= 0;
 58         end
 59         else begin
 60             cnt1 <= cnt1 + 1;
 61         end
 62     end
 63 end
 64 
 65 assign add_cnt1 = end_cnt0;
 66 assign end_cnt1 = add_cnt1 && cnt1 == 3 - 1; 
 67 
 68 //得多用一组时序逻辑对flag_add进行赋值，增加寄存器
 69 always @(posedge clk or negedge rst_n)begin
 70     if(!rst_n)begin
 71         flag_add <= 0;
 72     end
 73     else if(en1)begin
 74         flag_add <= 1;
 75     end
 76     else if(end_cnt0)begin //注意，变为0的条件不是end_cnt1
 77         flag_add <= 0;
 78     end
 79 end
 80 always @(posedge clk or negedge rst_n)begin
 81     if(!rst_n)begin
 82         dout <= 0;
 83     end
 84     else if(en1)begin
 85         dout <= z;
 86     end
 87     else if(end_cnt0)begin
 88         dout <= 0;
 89     end
 90 end
 91 
 92 always @(*)begin
 93     if(cnt1 == 0)begin
 94         z = 1;
 95     end
 96     else if(cnt1 == 1)begin
 97         z = 2;
 98     end
 99     else begin //省去if(cnt1 == 2) 
100         z = 3;
101     end
102 end
103 
104 endmodule

仿真波形结果一样：

 

标签：15,clk,练习,en1,计数器,rst,input,reg,dout
来源： https://www.cnblogs.com/wen2376/p/15914110.html