vivado implementation执行时候报错：Unsupported PLLE2_ADV connectivity.......

执行时候出错，

[DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wiz_0/inst/clk_in1 on the u_clk_wiz_0/inst/plle2_adv_inst/CLKIN1 pin of u_clk_wiz_0/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.

由提示信息可知，应该是配置clocking wizard出问题了。

解决办法：

选择PLL后，将source由“single ended clock capable pin”调为“global buffer”即可。再次implementation时候就不报错了。

标签：ADV,capable,clk,clock,connectivity,inst,报错,wiz
来源： https://www.cnblogs.com/amxiang/p/15710131.html