时序约束

目录

• • Defining Clock Constraints 时钟约束：
  • • Identifying Clock Sources
    • • Clock Networks Report 报告工程中的时钟网络：
      • Check Timing Report
    • Creating Primary Clocks
    • • Input Ports
      • Gigabit Transceiver Output Pins in 7 Series Devices
      • Certain Hardware Primitive Output Pins
    • Creating Generated Clocks
    • Adjusting Clock Characteristics
    • • Jitter
      • Additional Uncertainty
      • Clock Latency at the Source
      • MMCM or PLL External Feedback Loop Delay
  • Defining Clock Groups and CDC Constraints
  • Constraining Input and Output Ports (约束输入输出端口)
  • Specifying Timing Exceptions
  • • Timing Exceptions Guidelines
    • • Adding False Path Constraints

学习手册 UG949
对更加详细的约束信息参照 UG906 UG903

1.组织管理约束文件
对于简单的工程，我们可以按照下面的方法组织我们的约束文件：

• 直接采用一个约束文件；
• 物理约束+时序约束
• 物理约束+时序约束（综合）+ 时序约束（实现）

对于大型的项目或者是多个团队合作实现的约束可以采用下面的方法：

• 一个顶层的物理约束+一个顶层的时序约束+对每个IP的约束或者每个模块的时序约束

如果一个工程中存在多个约束文件，那么此时需要注意约束文件的编译顺序：

• 在工程模式下可以使用reorder_files tcl命令改变约束文件的编译顺序，
• 在非工程模式下约束文件的执行顺序直接由read_xdc和source 的顺序所决定。

ug949 P151 打开实际的工程进行测试

Defining Clock Constraints 时钟约束：

Identifying Clock Sources

Clock Networks Report 报告工程中的时钟网络：

其中包括可以报告未添加约束的时钟！！！
命令：

report_clock_networks

这个命令可以报告出未添加约束的时钟网络，
example:

Clock Networks Report

Constrained Clocks
-------------------

Clock clk_fpga_0 (50MHz)(endpoints: 0 clock, 1 nonclock)
PS7/FCLKCLK[0] (processing_system_i/processing_system7_0/inst/PS7_i)

Unconstrained Clocks
-------------------
Clock osc_clk (endpoints: 38 clock, 0 nonclock)
Port osc_clk

在上面的例子中可以看到在报告中已经指出哪些时钟已经添加了约束，哪一些没有添加约束（osc_clk）。

Check Timing Report

在这个报告中的no_clock 不懂

check_timing -override_defaults no_clock

result：

check_timing report

Table of Contents
-----------------
1. checking no_clock

1. checking no_clock
--------------------
 There are 38 register/latch pins with no clock driven by root clock pin: osc_clk (HIGH)

在上面的这个例子中我猜测这个no_clock 与我没有约束osc_clk 有关。后面添加一下约束后再测试一下。

Creating Primary Clocks

Input Ports

Constraint example:

create_clock -period 20.000 -name osc_clk -waveform {0.000 10.000} -add [get_ports osc_clk]

Gigabit Transceiver Output Pins in 7 Series Devices

如下图所示：
Constraint example:

create_clock -name txclk -period 6.667 [get_pins gt0/TXOUTCLK]

推荐：对于目标7系列设备的设计，Xilinx也建议定义 GT incoming clocks，因为Vivado工具计算GT输出引脚上的预期时钟，并比较这些时钟用户创建的时钟。如果时钟缺少或缺少GT的传入时钟，则该工具发出了机理方法检查警告。
对于目标UltraScale™设备的设计，Xilinx不建议在GT的输出上定义primary 时钟，因为GT时钟是自动的当相关的电路板输入时钟被占用时衍生。

Certain Hardware Primitive Output Pins

不推荐使用扇出的时钟进行约束![在这里插入图片描述](https://www.icode9.com/i/ll/?i=20210328193039209.png?,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzM5NTk3NDg5,size_16,color_FFFFFF,t_70

Creating Generated Clocks

生成的时钟是从称为主时钟的另一个现有时钟导出的时钟。它通常通过逻辑块在主时钟上执行的波形变换。

生成时钟分为自动生成时钟和用户自定义生成时钟：

• Auto-Derived Clocks
  Most generated clocks are automatically derived by the Vivado timing engine which recognizesthe clock modifying blocks (CMB) and the transformation they perform on the master clocks.In the Xilinx 7 series device family, the CMBs are:
  • MMCM*/ PLL*
  • BUFR
  • PHASER*
• User-Defined Generated Clocks
  例如用已经进行了时序约束的一个primary clock 通过一个逻辑产生一个二分频时钟，约束应该这样写：

  create_generated_clock -name clkDiv2 -divide_by 2 \
  -source [get_pins fd/C] [get_pins fd/Q]
  

Adjusting Clock Characteristics

Jitter

For jitter, it is best to use the default values used by the Vivado Design Suite. You can modify thedefault computation as follows:
• If a primary clock enters the device with a random jitter greater than zero, use theset_input_jitter command to specify the peak-to-peak jitter value in nanoseconds.
• To adjust the global jitter if the device power supply is noisy, use set_system_jitter.Xilinx does not recommend increasing the default system jitter value.For generated clocks, the jitter is derived from the master clock and the characteristics of theclock modifying block. You do not need to adjust these numbers.

Additional Uncertainty

For example, the margin on all intra-clock paths of the design clock clk0 needs to be tightenedby 500 ps to make the design more robust to noise for both setup and hold:

set_clock_uncertainty -from clk0 -to clk0 0.500

Clock Latency at the Source

MMCM or PLL External Feedback Loop Delay

Defining Clock Groups and CDC Constraints

example

create_clock -name clk_mode0 -period 10 [get_ports clkin]
create_clock -name clk_mode1 -period 13.334 -add [get_ports clkin]
set_clock_groups -physically_exclusive -group clk_mode0 -group clk_mode1

If the clk_mode0 and clk_mode1 clocks generate other clocks, the same constraint needs tobe applied to their generated clocks as well, which can be done as follows:

set_clock_groups -physically_exclusive \
-group [get_clocks -include_generated_clock clk_mode0] \
-group [get_clocks -include_generated_clock clk_mode1]

Global Constraints Between Clocks in Both Directions

When there is no need to limit the maximum latency, the clock groups can be used. Following isan example to ignore paths between clkA and clkB:

set_clock_groups -asynchronous -group clkA -group clkB

When two master clocks and their respective generated clocks form two asynchronous domainsbetween which all the paths are properly synchronized, the clock groups constraint can beapplied to several clocks at once:

set_clock_groups -asynchronous \
-group {clkA clkA_gen0 clkA_gen1 } \
-group {clkB clkB_gen0 clkB_gen1 }

Constraining Input and Output Ports (约束输入输出端口)

在工程中需要一些高级的参数设置，平时没有设置过，暂时跳过，后面遇到再补充……

Specifying Timing Exceptions

Timing Exceptions Guidelines

Adding False Path Constraints

标签：Clock,clk,clock,约束,clocks,时序,时钟
来源： https://www.cnblogs.com/amxiang/p/15650274.html