Verilog练习：HDLBits笔记16
作者：互联网
四、Sequential Logic
Building Larger Circuits
1、Counter with period 1000
Problem Statement：
Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.
module top_module (
input clk,
input reset,
output [9:0] q
);
reg[9:0]cnt;
always@(posedge clk)begin
if(reset)
cnt <= 10'd0;
else if(cnt == 10'd999)
cnt <= 10'd0;
else
cnt <= cnt + 10'd1;
end
assign q = cnt;
endmodule
2、4-bit shift register and down counter
Problem Statement：
Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q);
always@(posedge clk)begin
case({shift_ena,count_ena})
2'b01 : q <= q - 1'b1;
2'b10 : q <= {q[2:0],data};
endcase
end
endmodule
3、Sequence 1101 recognizer
Problem Statement：
Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.
module top_module (
input clk,
input reset,
input data,
output start_shifting
);
parameter mon = 3'd1,
s0 = 3'd2,
s1 = 3'd3,
s2 = 3'd4,
s3 = 3'd5;
reg[2:0]current_state;
reg[2:0]next_state;
always@(posedge clk)begin
if(reset)
current_state <= mon;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= mon;
else
case(current_state)
mon : next_state <= data ? s0 : mon;
s0 : next_state <= data ? s1 : mon;
s1 : next_state <= data ? s1 : s2;
s2 : next_state <= data ? s3 : mon;
s3 : next_state <= s3;
default : next_state <= mon;
endcase
end
always@(posedge clk)begin
if(reset)
start_shifting <= 1'b0;
else
case(next_state)
s3 : start_shifting <= 1'b1;
default : start_shifting <= 1'b0;
endcase
end
endmodule
4、Enable shift register
Problem Statement：
As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.
Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).
module top_module (
input clk,
input reset,
output shift_ena);
reg[2:0]cnt;
always@(posedge clk)begin
if(reset)
shift_ena <= 1'b1;
else if(cnt == 3'd3)
shift_ena <= 1'b0;
else
shift_ena <= shift_ena;
end
always@(posedge clk)begin
if(reset)
cnt <= 3'd0;
else if(shift_ena)
cnt <= cnt + 1'd1;
else
cnt <= cnt;
end
endmodule
5、The complete FSM
Problem Statement：
We want to create a timer that:
- is started when a particular pattern (1101) is detected,
- shifts in 4 more bits to determine the duration to delay,
- waits for the counters to finish counting, and
- notifies the user and waits for the user to acknowledge the timer.
In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.
The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.
After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.
At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).
The state machine should reset into a state where it begins searching for the input sequence 1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.
module top_module (
input clk,
input reset,
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
parameter mon = 4'd0,
s0 = 4'd1,
s1 = 4'd2,
s2 = 4'd3,
shift = 4'd4,
count = 4'd5,
finish = 4'd6;
reg[3:0]current_state;
reg[3:0]next_state;
reg[2:0]cnt;
always@(posedge clk)begin
if(reset)
cnt <= 3'd0;
else if(next_state == shift)
cnt <= cnt + 1'd1;
else if(cnt == 3'd4)
cnt <= 3'd0;
else
cnt <= cnt;
end
always@(posedge clk)begin
if(reset)
current_state <= mon;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= mon;
else
case(current_state)
mon : next_state <= data ? s0 : mon;
s0 : next_state <= data ? s1 : mon;
s1 : next_state <= data ? s1 : s2;
s2 : next_state <= data ? shift : mon;
shift : begin
if(cnt == 3'd4)
next_state <= count;
else
next_state <= shift;
end
count : next_state <= done_counting ? finish : count;
finish : next_state <= ack ? mon : finish;
default : next_state <= mon;
endcase
end
always@(posedge clk)begin
if(reset)begin
shift_ena <= 1'b0;
counting <= 1'b0;
done <= 1'b0;
end
else
case(next_state)
shift : begin
shift_ena <= 1'b1;
counting <= 1'b0;
done <= 1'b0;
end
count : begin
shift_ena <= 1'b0;
counting <= 1'b1;
done <= 1'b0;
end
finish : begin
shift_ena <= 1'b0;
counting <= 1'b0;
done <= 1'b1;
end
default : begin
shift_ena <= 1'b0;
counting <= 1'b0;
done <= 1'b0;
end
endcase
end
endmodule
6、The complete timer
Problem Statement：
We want to create a timer with one input that:
- is started when a particular input pattern (1101) is detected,
- shifts in 4 more bits to determine the duration to delay,
- waits for the counters to finish counting, and
- notifies the user and waits for the user to acknowledge the timer.
The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].
After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).
At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).
The circuit should reset into a state where it begins searching for the input sequence 1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.
module top_module (
input clk,
input reset,
input data,
output [3:0] count,
output counting,
output done,
input ack
);
parameter mon = 3'd0,
s0 = 3'd1,
s1 = 3'd2,
s2 = 3'd3,
shift = 3'd4,
cnt_num = 3'd5,
finish = 3'd6;
reg[2:0]current_state;
reg[2:0]next_state;
reg[1:0]cnt_shift;
reg[3:0]shift_data;
reg[15:0]cnt;
always@(posedge clk)begin
if(reset)
current_state <= mon;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= mon;
else
case(current_state)
mon : next_state <= data ? s0 : mon;
s0 : next_state <= data ? s1 : mon;
s1 : next_state <= data ? s1 : s2;
s2 : next_state <= data ? shift : mon;
shift : begin
if(cnt_shift == 2'd3)
next_state <= cnt_num;
else
next_state <= shift;
end
cnt_num : next_state <= cnt ? cnt_num : finish;
finish : next_state <= ack ? mon : finish;
default : next_state <= mon;
endcase
end
assign count = cnt/1000;
assign counting = (current_state == cnt_num);
assign done = (current_state == finish);
always@(posedge clk)begin
if(reset)
cnt_shift <= 2'b0;
else if(current_state == shift)
cnt_shift <= cnt_shift + 1'b1;
else if(cnt_shift == 2'd3)
cnt_shift <= 2'b0;
else
cnt_shift <= cnt_shift;
end
always@(*)begin
if(current_state == shift)
case(cnt_shift)
2'd0: shift_data[3] <= data;
2'd1: shift_data[2] <= data;
2'd2: shift_data[1] <= data;
2'd3: shift_data[0] <= data;
default:;
endcase
else
shift_data = 4'd0;
end
always @(posedge clk)begin
if(reset)
cnt <= 16'd0;
else if(current_state == shift)
cnt <= (shift_data + 1'b1) * 1000-1'd1;
else if(current_state == cnt_num)
cnt <= cnt - 1'd1;
else
cnt <= cnt;
end
endmodule
7、The complete timer
Problem Statement：
Given the following state machine with 3 inputs, 3 outputs, and 10 states:
Derive next-state logic equations and output logic equations by inspection assuming the following one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) = (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)
Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
Write code that generates the following equations:
- B3_next -- next-state logic for state B1
- S_next
- S1_next
- Count_next
- Wait_next
- done -- output logic
- counting
- shift_ena
module top_module(
input d,
input done_counting,
input ack,
input [9:0] state,
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
parameter s = 0,
s1 = 1,
s11 = 2,
s110 = 3,
b0 = 4,
b1 = 5,
b2 = 6,
b3 = 7,
count = 8,
finish = 9;
assign B3_next = state[b2];
assign S_next = (state[s] & ~d) | (state[s1] & ~d) | (state[s110] & ~d) | (state[finish] & ack) ;
assign S1_next = state[s] & d;
assign Count_next = state[b3] | (state[count] & ~done_counting);
assign Wait_next = (state[count] & done_counting) | (state[finish] & ~ack);
assign done = state[finish];
assign counting = state[count];
assign shift_ena = state[b0] | state[b1] | state[b2] |state[b3];
endmodule
标签：reset,HDLBits,shift,16,next,state,Verilog,output,input 来源： https://blog.csdn.net/WinstonQQM/article/details/121603300