RISC-CPU设计（七）：算术运算器模块（ALU）设计

1.算术运算器模块的作用

        算术运算器模块根据输入的8种不同操作码（来自指令寄存器输出的最高三位）分别实现对应的加、与、异或、跳转等基本操作运算。利用这几种基本运算可以实现很多种其它运算以及逻辑判断等操作。

2.模块端口图

 3.端口功能描述

        DATA和ACCUM分别是来自累加器和数据控制器的输出，OPCODE是来自指令寄存器输出的高三位指令信号，由时钟控制模块产生的alu_clk信号控制下，实现八种指令对应的不同操作，由ALU_OUT端口输出。八种指令及其对应操作见：RISC-CPU设计（六）：RISC-CPU的寻址方式和指令系统_weixin_43701504的博客-CSDN博客

4.Verilog代码

module alu (    
    data        ,
    accum       ,
    alu_ena     ,
    opcode      ,
    zero        ,
    alu_out
);
    
    input       [7: 0]  data        ;
    input       [7: 0]  accum       ;
    input               alu_ena     ;
    input       [2: 0]  opcode      ;
    output              zero        ;
    output  reg [7: 0]  alu_out     ;

// opcode[2: 0] has 8 values, refers to 8 operations as follow:
    parameter   HLT  = 3'b000   ,
                SKZ  = 3'b001   ,
                ADD  = 3'b010   ,
                ANDD = 3'b011   ,
                XORR = 3'b100   ,
                LDA  = 3'b101   ,
                STO  = 3'b110   ,
                JMP  = 3'b111   ;

    assign zero = !accum    ;

    always @( * ) begin
        if ( alu_ena ) begin
            casex ( opcode )
                HLT :   alu_out <= accum        ;
                SKZ :   alu_out <= accum        ;
                ADD :   alu_out <= data + accum ;
                ANDD:   alu_out <= data & accum ;
                XORR:   alu_out <= data ^ accum ;
                LDA :   alu_out <= data         ;
                STO :   alu_out <= accum        ;
                JMP :   alu_out <= accum        ;
                default:alu_out <= 8'bxxxx_xxxx ;    
            endcase
        end
    end

endmodule

testbench:

`timescale 1ns / 1ps
//
// change the value of opcode,watch the value of alu_out & zero
//

module alu_tb();

reg     [7:0]   data    ;
reg     [7:0]   accum   ;
reg             alu_ena ;
reg     [2:0]   opcode  ;
wire            zero    ;
wire    [7:0]   alu_out ;

alu u5 (    
    .data        ( data     ),
    .accum       ( accum    ),
    .alu_ena     ( alu_ena  ),
    .opcode      ( opcode   ),
    .zero        ( zero     ),
    .alu_out     ( alu_out  )
);

initial begin
    alu_ena = 1;
    data    = 8'b0101_0011;
    accum   = 8'b1010_0011;
 // ---------HLT
    opcode  = 3'b000;
    #100;
    // ---------SKZ
    opcode  = 3'b001;
    #100;
     // ---------ADD
    opcode  = 3'b010;
    #100;
    // ---------AND
    opcode  = 3'b011;
    #100;
     // ---------XOR
    opcode  = 3'b100;
    #100;
    // ---------LDA
    opcode  = 3'b101;
    #100;
     // ---------STO
    opcode  = 3'b110;
    #100;
    // ---------JMP
    opcode  = 3'b111;
    #100;
    // ------zero
    accum   = 8'b0000_0000;
    #100;
    // disable ena
    accum   = 8'b1010_0011;
    #100;
    alu_ena = 0;
    #200;
end

endmodule

仿真图：

标签：ena,ALU,---------,RISC,opcode,100,alu,accum,CPU
来源： https://blog.csdn.net/weixin_43701504/article/details/121129968