学习目标

• Know the difference between cto cells and common cells. 
• Can determine at which stage the cto cells are inserted in the flow.

学习内容 

• CTO Cells Selection
• CTO cells naming rules

Clock tree systhesis 

Clock tree systhesis 2步：

CTS: clock tree synthesis,  focus on fixing clock tree logic drc

• Maximum load capacitance
• Maximum fanout
• Maximum transition
• Maximum buffer levels

CTO: clock tree optimization    

•  Maximum skew
•  Min/Max insertion delay

 Logic drc opt

 CTO Cell

 CTO是 Clock Tree Optimization

 初始状态在CTO开始之前报告

CTS Cells Selection 

 cts cells 和 common cells之间的差别

• CTS cells 是CTS专用的cell。 
• 与common cellls相比,  cts cells'的rising transition time 和 falling transition time 是平衡的。
• cts cells 的Ref name 是以 CK/DCCK开头的
   

CTO  techniques 

• Delay insertion:- It will improve hold time.
• Buffering:- It will improve setup time.
• Buffer relocation:- Reduce skew and insertion delay.
• Level adjustment:- Adjust a level of clock pins to a higher or lower
• Gate sizing:- It may decrease the delay.
• To fix max transition add buffers and to fix max capacitance decrease the net  length,cloning.

CTS Cells Naming Rules

CTS和CTO过程中的cell命名 

标签：CTS,Introduction,cells,clock,tree,APR23,cell,time,CTO
来源： https://blog.csdn.net/weixin_41788560/article/details/120926827