来自网站

1.网站说明-tutorial

• This SystemVerilog tutorial is written to help engineers with background in Verilog/VHDL to get jump start in SystemVerilog design and Verification. In case you find any mistake, please do let me know. I always love to hear about mistakes in my website.

• As such this tutorial assumes that, you are already familiar with Verilog and bit of C/C++ language. If you are not well versed with verilog, you can refer to verilog section or go through the Verilog basics tutorial below.

• Currently this website is getting more than 3 million hits every month.
  总结就是网站帮助具有Verilog或VHDL背景的人员快速学习使用SystemVerilog来设计和验证.假想读者已经熟悉Verilog或者C/C++，否则可以先看看Verilog基础部分——verilog basic

2.SystemVerilog

• Verilog 1995 version has been in market for a very long time. IEEE extended the features of Verilog 1995 and released it as Verilog 2001. But this was no good for verification engineers, so verifcation engineers had to use languages like "e", VERA, Testbuider. It was rather painfull to have two language, one for design and other for verification. SystemVerilog combines the Verification capabilties of HVL (Hardware Verification Language) with ease of Verilog to provide a single platform for both design and verification.

• ==Anyone with background of C++, or OO programming language will feel at home with SystemVerilog. But on other hand if you have been thinking C or C++ is not required, then you may be shocked to know that SystemVerilog is very much like C++. ==

• *Now IEEE has accepted the SystemVerilog, and it is called 1800-2005 standard. *

Some of the new features in SystemVerilog are as listed below.

• C type data types like int, typedef, struct, union, enum.
• Dynamic data types : struct, classes, dynamic queues, dynamic arrays.
• New operators and built in methods.
• Enhanced flow control like, foreach, return, break, continue.
• Semaphores, mailboxes, event extensions.
• classes for object oriented programming.面向对象编程
• Assertions.断言
• Coverage.覆盖
• VPI extensions.

2.1Verilog Basic

• 主要回顾verilog最基础的部分，为SV入门必备

Verilog介绍

• Every new learner's dream is to understand Verilog in one day, at least enough to use it. The next few pages are my attempt to make this dream a reality. There will be some theory and examples followed by some exercises. This tutorial will not teach you how to program; it is designed for those with some programming experience. Even though Verilog executes different code blocks concurrently as opposed to the sequential execution of most programming languages, there are still many parallels. Some background in digital design is also helpful.不同于大多数编程语言，verilog语言中有许多并行执行的语句，有数字设计背景将有助于学习理解
• Life before Verilog was a life full of schematics. Every design, regardless of complexity, was designed through schematics. They were difficult to verify and error-prone, resulting in long, tedious development cycles of design, verification... design, verification... design, verification... Verilog语言出现之前，设计中多是原理图设计，对验证和错误检测带来了很大困难，从而导致开发周期很长

When Verilog arrived, we suddenly had a different way of thinking about logic circuits. The Verilog design cycle is more like a traditional programming one, and it is what this tutorial will walk you through. **Here's how it goes: **

• Specifications (specs) 协议
• High level design 高层次设计
• Low level (micro) design 低层次设计
• RTL coding RTL代码
• Verification 验证
• Synthesis. 综合

2.2Specifications

For this tutorial, we'll be building a two agent arbiter: a device that selects among two agents competing for mastership. Here are some specs we might write up.

• Two agent arbiter.
• Active high asynchronous reset. 高电平异步复位
• Fixed priority, with agent 0 having priority over agent 1 优先级
• Grant will be asserted as long as request is asserted. 发出请求时输出grant断言
  Once we have the specs, we can draw the block diagram, which is basically an abstraction of the data flow through a system (what goes into or comes out of the black boxes?). Since the example that we have taken is a simple one, we can have a block diagram as shown below. We don't worry about what's inside the magical black boxes just yet.

2.3Block diagram of arbiter

• Now, if we were designing this machine without Verilog, the standard procedure would dictate that we draw a state machine. From there, we'd make a truth table with state transitions for each flip-flop. And after that we'd draw Karnaugh maps, and from K-maps we could get the optimized circuit. This method works just fine for small designs, but with large designs this flow becomes complicated and error prone. This is where Verilog comes in and shows us another way.从顶层模块直接设计状态机容易出错，将顶层模块划分为若干子模块可以简化设计

2.4Low level design

Each of the circles represents a state that the machine can be in. Each state corresponds to an output. The arrows between the states are state transitions, labeled by the event that causes the transition. For instance, the leftmost orange arrow means that if the machine is in state GNT0 (outputting the signal that corresponds to GNT0) and receives an input of !req_0, the machine moves to state IDLE and outputs the signal that corresponds to that. This state machine describes all the logic of the system that you'll need. The next step is to put it all in Verilog.

Each of the circles represents a state that the machine can be in. Each state corresponds to an output. The arrows between the states are state transitions, labeled by the event that causes the transition. For instance, the leftmost orange arrow means that if the machine is in state GNT0 (outputting the signal that corresponds to GNT0) and receives an input of !req_0, the machine moves to state IDLE and outputs the signal that corresponds to that. This state machine describes all the logic of the system that you'll need.* The next step is to put it all in Verilog.*=详细的介绍看网站,=）

2.5两种设计方法

• 第一种设计方法是采用状态机设计

// 方法2 采用状态机实现
module arbiter_1 (
	input clk,
	input reset,//high activate asynchronous
	input req_0,req_1,//agent 0 having priority over agent 1
	output reg gnt_0,gnt_1
);

reg [2:0] state,next_state;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100;
always @(posedge clk or posedge reset) begin
	if (reset) begin
		state <= IDLE;
	end
	else begin
		state <= next_state;
	end
end	
always @(*) begin
	case (state)
		IDLE: begin if(req_0==1'b1) next_state = GNT0; 
			  else if(req_1==1'b1) next_state = GNT1;
			  else next_state = IDLE; end
		GNT0:begin if(req_0==1'b1) next_state = GNT0; 
			//  else if(req_1==1'b1) next_state = GNT1;
			 else next_state = IDLE;end
		GNT1:begin if(req_1==1'b1) next_state = GNT1; 
			//  else if(req_1==1'b1) next_state = GNT1;
			 else next_state = IDLE;end
		default:begin next_state = IDLE; end
	endcase
end

always @(*) begin
	if(state == GNT0)begin
		gnt_0 = 1'b1;
		gnt_1 = 1'b0;
	end
	else if(state == GNT1)begin
		gnt_1 = 1'b1;
		gnt_0 = 1'b0;
	end
	else begin
		gnt_0 = 1'b0;
		gnt_1 = 1'b0;
	end	
end

endmodule

• 仿真图：
  
• 在quartus II里面生成的状态图
  
• 第二种采用普通写法
  // 方法2

module arbiter (
	input clk,
	input reset,//high activate asynchronous
	input req_0,req_1,//agent 0 having priority over agent 1
	output reg gnt_0,gnt_1
);
always @(posedge clk or posedge reset) begin
	if (reset==1'b1) begin
		gnt_0 <= 1'b0;
		gnt_1 <= 1'b0;
	end
	else if(req_0==1'b1)begin
		gnt_0 = 1'b1;
		gnt_1 = 1'b0;
	end
	else if(req_1 == 1'b1)begin
		gnt_1= 1'b1;
		gnt_0= 1'b0;
	end
	else begin
	   		gnt_1= 1'b0;
            gnt_0= 1'b0;
	end
	
end
endmodule

标签：agent,machine,state,design,Tutorial,SystemVerilog,Verilog
来源： https://www.cnblogs.com/waqdgstd/p/15304032.html