基于FPGA的抢答器设计毕设论文

1、抢答判别模块
module qiang_da_pan_bie( clr, en, a, b, c, d, led_a, led_b ,led_c ,led_d, led_t,l ed_f);
input clr, en, a ,b ,c, d;
output led_a,led_b,led_c,led_d;
output [3:0] led_t;
output [3:0] led_f;
reg [3:0] states;            //zan cun a,b,c,d si zu zhuang tai
reg led_a,led_b,led_c,led_d;
reg [3:0] led_t,led_f;
initial
    begin
	   states={d, c, b, a};
	 end
always @ (*)
	begin
		 if(clr ==1)
			begin
				led_f=4'b0000;led_t=4'b0000;
			end
		else 
		   begin			 
				if((a==1)&&(b==0)&&(c==0)&&(d==0))	
					states<=4'b0001;			
				else if((a==0)&&(b==1)&&(c==0)&&(d==0))
					states<=4'b0010;
				else if((a==0)&&(b==0)&&(c==1)&&(d==0))
					states<=4'b0100;
				else if((a==0)&&(b==0)&&(c==0)&&(d==1))
					states<=4'b1000;
				else states<=states;
			end
			  if(en==0)			  
				begin			
					if (states==4'b0001)
						begin
							{led_d,led_c,led_b,led_a}<=states;
							led_f<=states;led_t<=4'b0001;
						end
					if (states==4'b0010)
						begin
							{led_d,led_c,led_b,led_a}<=states;
							led_f<=states;led_t<=4'b0010;
						end
					if (states==4'b0100)
						begin
							{led_d,led_c,led_b,led_a}<=states;
							led_f<=states;led_t<=4'b0011;
						end		
					if (states==4'b1000)
						begin
							{led_d,led_c,led_b,led_a}<=states;
							led_f<=states;led_t<=4'b0100;
						end		
				end
			if (en==1)
				begin
					if (states==4'b0001)
						begin
							{led_d,led_c,led_b,led_a}<=states;					
							led_t<=4'b0001;
						end
					if (states==4'b0010)
						begin
							{led_d,led_c,led_b,led_a}<=states;					
							led_t<=4'b0010;
						end
					if (states==4'b0100)
						begin
							{led_d,led_c,led_b,led_a}<=states;
							led_t<=4'b0011;
						end
					if (states==4'b1000)
						begin
							{led_d,led_c,led_b,led_a}<=states;
							led_t<=4'b0100;
						end
				end	
	end
endmodule

链接：https://pan.baidu.com/s/1DgDZDAXgkZinHT1_OUZxJg
提取码：mvbo

标签：begin,毕设,led,FPGA,reg,&&,output,抢答器,clr
来源： https://blog.csdn.net/weixin_46018613/article/details/119294502