2021-07-25

单bit跨时钟域脉冲同步器，快时钟域到慢时钟域脉冲同步

模块

module mul_clk(
input       clk_a   ,
input       clk_b   ,
input       rst_n   ,
input       din     ,
output reg dout
);

reg din_dely = 0;
reg feedback = 0;
	
always@(posedge clk_a or negedge rst_n)
begin
	if(

标签：25,din,07,clk,2021,rst,input,reg,时钟
来源： https://blog.csdn.net/ylfxhdjn/article/details/119080696