VHDL VGA 时钟处理 转盘形式 源代码
作者：互联网
library ieee;
use ieee.std_logic_1164.all;
entity vga_display is
port(rst_n:in std_logic ;
clk :in std_logic ;
right_a:in std_logic;
left_a:in std_logic;
up_a:in std_logic;
down_a:in std_logic;
xpos:in integer;
ypos:in integer;
LED : IN std_logic_vector(3 downto 0);
data:out std_logic_vector(2 downto 0)
);
end vga_display;
architecture a of vga_display is
constant h_disp:integer:=800;
constant red : std_logic_vector:=“100”;
constant yellow: std_logic_vector:=“110”;
constant green: std_logic_vector:=“010”;
constant gry: std_logic_vector:=“111”;
signal color:integer:=0;
signal dianshu:integer:=9;
signal LEDAS: std_logic_vector(3 downto 0):=“1111”;
signal xiaoshi:integer:=0;
signal fen:integer:=0;
signal miao:integer:=0;
signal clkk:integer:=0;
signal sinx:integer:=0;
signal siny:integer:=0;
signal sinxa:integer:=0;
signal sinya:integer:=0;
signal sinxb:integer:=0;
signal sinyb:integer:=0;
signal kongzhian:integer:=0;
signal kongzhiana:integer:=0;
begin
process(rst_n,clk)
begin
if rst_n=‘0’ then
data<=“000”;
elsif clk’event and clk=‘1’ then
if right_a='0' and kongzhian=0 then
fen<=fen+1;kongzhian<=1;
end if;
if right_a='1' and kongzhian=1 then
kongzhian<=0;
end if;
if up_a='0' and kongzhiana=0 then
xiaoshi<=xiaoshi+1;kongzhiana<=1;
end if;
if up_a='1' and kongzhiana=1 then
kongzhiana<=0;
end if;
if LED="0001" AND LEDAS/=LED THEN fen<=fen+1;LEDAS<=LED;
end if;
if LED="0010" AND LEDAS/=LED THEN fen<=fen+1;LEDAS<=LED;
end if;
if LED="0100" AND LEDAS/=LED THEN xiaoshi<=xiaoshi+1;LEDAS<=LED;
end if;
if LED="0000" AND LEDAS/=LED THEN xiaoshi<=xiaoshi+1;LEDAS<=LED;
end if;
clkk<=clkk+1;
if clkk=40000000 then clkk<=0; miao<=miao+1;
end if;
if miao=60 then miao<=0;fen<=fen+1;
end if;
if fen=60 then fen<=0;xiaoshi<=xiaoshi+1;
end if;
if xiaoshi=12 then xiaoshi<=0;
end if;
if xpos>390 and xpos<410 and ypos>90 and ypos<110 then
color<=1;
elsif xpos>190 and xpos<210 and ypos>290 and ypos<310 then
color<=1;
elsif xpos>590 and xpos<610 and ypos>290 and ypos<310 then
color<=1;
elsif xpos>390 and xpos<410 and ypos>490 and ypos<510 then
color<=1;
elsif xpos>495 and xpos<505 and ypos>122 and ypos<132 then
color<=1;
elsif xpos>568 and xpos<578 and ypos>195 and ypos<205 then
color<=1;
elsif xpos>495 and xpos<505 and ypos>468 and ypos<478 then
color<=1;
elsif xpos>568 and xpos<578 and ypos>395 and ypos<405 then
color<=1;
elsif xpos>295 and xpos<305 and ypos>122 and ypos<132 then
color<=1;
elsif xpos>222 and xpos<232 and ypos>195 and ypos<205 then
color<=1;
elsif xpos>295 and xpos<305 and ypos>468 and ypos<478 then
color<=1;
elsif xpos>222 and xpos<232 and ypos>395 and ypos<405 then
color<=1;
elsif xpos>396 and xpos<404 and ypos>296 and ypos<304 then
color<=4;
else
color<=0;
end if;
if xiaoshi=0 then sinxb<=0; sinyb<=200;
elsif xiaoshi=1 then sinxb<=99; sinyb<=173;
elsif xiaoshi=2 then sinxb<=173; sinyb<=100;
elsif xiaoshi=3 then sinxb<=199; sinyb<=0;
elsif xiaoshi=4 then sinxb<=173; sinyb<=-99;
elsif xiaoshi=5 then sinxb<=100; sinyb<=-173;
elsif xiaoshi=6 then sinxb<=0; sinyb<=-199;
elsif xiaoshi=7 then sinxb<=-99; sinyb<=-173;
elsif xiaoshi=8 then sinxb<=-173; sinyb<=-100;
elsif xiaoshi=9 then sinxb<=-199; sinyb<=0;
elsif xiaoshi=10 then sinxb<=-173; sinyb<=99;
elsif xiaoshi=11 then sinxb<=-100; sinyb<=173;
end if;
for n in 1 to dianshu-3 loop
if xpos>396+sinxb*n/dianshu and xpos<404+sinxb*n/dianshu and ypos>296-sinyb*n/dianshu and ypos<304-sinyb*n/dianshu then
color<=3;exit;
end if;
end loop;
if fen=0 then sinxa<=0; sinya<=200;
elsif fen=1 then sinxa<=20; sinya<=198;
elsif fen=2 then sinxa<=41; sinya<=195;
elsif fen=3 then sinxa<=61; sinya<=190;
elsif fen=4 then sinxa<=81; sinya<=182;
elsif fen=5 then sinxa<=99; sinya<=173;
elsif fen=6 then sinxa<=117; sinya<=161;
elsif fen=7 then sinxa<=133; sinya<=148;
elsif fen=8 then sinxa<=148; sinya<=133;
elsif fen=9 then sinxa<=161; sinya<=117;
elsif fen=10 then sinxa<=173; sinya<=100;
elsif fen=11 then sinxa<=182; sinya<=81;
elsif fen=12 then sinxa<=190; sinya<=61;
elsif fen=13 then sinxa<=195; sinya<=41;
elsif fen=14 then sinxa<=198; sinya<=20;
elsif fen=15 then sinxa<=199; sinya<=0;
elsif fen=16 then sinxa<=198; sinya<=-20;
elsif fen=17 then sinxa<=195; sinya<=-41;
elsif fen=18 then sinxa<=190; sinya<=-61;
elsif fen=19 then sinxa<=182; sinya<=-81;
elsif fen=20 then sinxa<=173; sinya<=-99;
elsif fen=21 then sinxa<=161; sinya<=-117;
elsif fen=22 then sinxa<=148; sinya<=-133;
elsif fen=23 then sinxa<=133; sinya<=-148;
elsif fen=24 then sinxa<=117; sinya<=-161;
elsif fen=25 then sinxa<=100; sinya<=-173;
elsif fen=26 then sinxa<=81; sinya<=-182;
elsif fen=27 then sinxa<=61; sinya<=-190;
elsif fen=28 then sinxa<=41; sinya<=-195;
elsif fen=29 then sinxa<=20; sinya<=-198;
elsif fen=30 then sinxa<=0; sinya<=-199;
elsif fen=31 then sinxa<=-20; sinya<=-198;
elsif fen=32 then sinxa<=-41; sinya<=-195;
elsif fen=33 then sinxa<=-61; sinya<=-190;
elsif fen=34 then sinxa<=-81; sinya<=-182;
elsif fen=35 then sinxa<=-99; sinya<=-173;
elsif fen=36 then sinxa<=-117; sinya<=-161;
elsif fen=37 then sinxa<=-133; sinya<=-148;
elsif fen=38 then sinxa<=-148; sinya<=-133;
elsif fen=39 then sinxa<=-161; sinya<=-117;
elsif fen=40 then sinxa<=-173; sinya<=-100;
elsif fen=41 then sinxa<=-182; sinya<=-81;
elsif fen=42 then sinxa<=-190; sinya<=-61;
elsif fen=43 then sinxa<=-195; sinya<=-41;
elsif fen=44 then sinxa<=-198; sinya<=-20;
elsif fen=45 then sinxa<=-199; sinya<=0;
elsif fen=46 then sinxa<=-198; sinya<=20;
elsif fen=47 then sinxa<=-195; sinya<=41;
elsif fen=48 then sinxa<=-190; sinya<=61;
elsif fen=49 then sinxa<=-182; sinya<=81;
elsif fen=50 then sinxa<=-173; sinya<=99;
elsif fen=51 then sinxa<=-161; sinya<=117;
elsif fen=52 then sinxa<=-148; sinya<=133;
elsif fen=53 then sinxa<=-133; sinya<=148;
elsif fen=54 then sinxa<=-117; sinya<=161;
elsif fen=55 then sinxa<=-100; sinya<=173;
elsif fen=56 then sinxa<=-81; sinya<=182;
elsif fen=57 then sinxa<=-61; sinya<=190;
elsif fen=58 then sinxa<=-41; sinya<=195;
elsif fen=59 then sinxa<=-20; sinya<=198;
end if;
for n in 1 to dianshu-1 loop
if xpos>397+sinxa*n/dianshu and xpos<403+sinxa*n/dianshu and ypos>297-sinya*n/dianshu and ypos<303-sinya*n/dianshu then
color<=2;exit;
end if;
end loop;
if miao=0 then sinx<=0; siny<=200;
elsif miao=1 then sinx<=20; siny<=198;
elsif miao=2 then sinx<=41; siny<=195;
elsif miao=3 then sinx<=61; siny<=190;
elsif miao=4 then sinx<=81; siny<=182;
elsif miao=5 then sinx<=99; siny<=173;
elsif miao=6 then sinx<=117; siny<=161;
elsif miao=7 then sinx<=133; siny<=148;
elsif miao=8 then sinx<=148; siny<=133;
elsif miao=9 then sinx<=161; siny<=117;
elsif miao=10 then sinx<=173; siny<=100;
elsif miao=11 then sinx<=182; siny<=81;
elsif miao=12 then sinx<=190; siny<=61;
elsif miao=13 then sinx<=195; siny<=41;
elsif miao=14 then sinx<=198; siny<=20;
elsif miao=15 then sinx<=199; siny<=0;
elsif miao=16 then sinx<=198; siny<=-20;
elsif miao=17 then sinx<=195; siny<=-41;
elsif miao=18 then sinx<=190; siny<=-61;
elsif miao=19 then sinx<=182; siny<=-81;
elsif miao=20 then sinx<=173; siny<=-99;
elsif miao=21 then sinx<=161; siny<=-117;
elsif miao=22 then sinx<=148; siny<=-133;
elsif miao=23 then sinx<=133; siny<=-148;
elsif miao=24 then sinx<=117; siny<=-161;
elsif miao=25 then sinx<=100; siny<=-173;
elsif miao=26 then sinx<=81; siny<=-182;
elsif miao=27 then sinx<=61; siny<=-190;
elsif miao=28 then sinx<=41; siny<=-195;
elsif miao=29 then sinx<=20; siny<=-198;
elsif miao=30 then sinx<=0; siny<=-199;
elsif miao=31 then sinx<=-20; siny<=-198;
elsif miao=32 then sinx<=-41; siny<=-195;
elsif miao=33 then sinx<=-61; siny<=-190;
elsif miao=34 then sinx<=-81; siny<=-182;
elsif miao=35 then sinx<=-99; siny<=-173;
elsif miao=36 then sinx<=-117; siny<=-161;
elsif miao=37 then sinx<=-133; siny<=-148;
elsif miao=38 then sinx<=-148; siny<=-133;
elsif miao=39 then sinx<=-161; siny<=-117;
elsif miao=40 then sinx<=-173; siny<=-100;
elsif miao=41 then sinx<=-182; siny<=-81;
elsif miao=42 then sinx<=-190; siny<=-61;
elsif miao=43 then sinx<=-195; siny<=-41;
elsif miao=44 then sinx<=-198; siny<=-20;
elsif miao=45 then sinx<=-199; siny<=0;
elsif miao=46 then sinx<=-198; siny<=20;
elsif miao=47 then sinx<=-195; siny<=41;
elsif miao=48 then sinx<=-190; siny<=61;
elsif miao=49 then sinx<=-182; siny<=81;
elsif miao=50 then sinx<=-173; siny<=99;
elsif miao=51 then sinx<=-161; siny<=117;
elsif miao=52 then sinx<=-148; siny<=133;
elsif miao=53 then sinx<=-133; siny<=148;
elsif miao=54 then sinx<=-117; siny<=161;
elsif miao=55 then sinx<=-100; siny<=173;
elsif miao=56 then sinx<=-81; siny<=182;
elsif miao=57 then sinx<=-61; siny<=190;
elsif miao=58 then sinx<=-41; siny<=195;
elsif miao=59 then sinx<=-20; siny<=198;
end if;
for n in 1 to dianshu loop
if xpos>398+sinx*n/dianshu and xpos<402+sinx*n/dianshu and ypos>298-siny*n/dianshu and ypos<302-siny*n/dianshu then
color<=1;exit;
end if;
end loop;
end if;
if color=1 then data<=red;
elsif color=2 then data<=yellow;
elsif color=3 then data<=green;
elsif color=4 then data<=gry;
else data<="000";
end if;
end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
entity vga_drive is
port(
rst_n:in std_logic;
clk :in std_logic;
xpos:out integer;
ypos:out integer;
data:in std_logic_vector(2 downto 0);
vga_h:out std_logic ;
vga_v:out std_logic ;
vga_r:out std_logic ;
vga_g:out std_logic ;
vga_b:out std_logic
);
end vga_drive;
architecture a of vga_drive is
constant h_sync:integer :=128;
constant v_sync:integer :=4;
signal cnt_h:integer;
signal cnt_v:integer;
signal vga_en:std_logic;
begin
process(rst_n,clk)
begin
if rst_n=‘0’ then cnt_h <=0;
elsif clk'event and clk='1' then
if cnt_h<1055 then cnt_h<=cnt_h+1;
else cnt_h<=0;
end if;
end if;
end process;
vga_h<=‘0’ when cnt_h<h_sync else’1’;
process(rst_n,clk)
begin
if rst_n=‘0’ then cnt_v<=0;
elsif clk 'event and clk=‘1’ then
if cnt_h =1055 then
if cnt_v<627 then cnt_v<=cnt_v+1;
else cnt_v<=0;
end if;
end if;
end if;
end process;
vga_v<=‘0’ when cnt_v<v_sync else’1’;
xpos <=cnt_h-(128+88);
ypos <=cnt_v-(4+23);
vga_r<=data(2) when vga_en=‘1’ else ‘0’;
vga_g<=data(1) when vga_en=‘1’ else ‘0’;
vga_b<=data(0) when vga_en=‘1’ else ‘0’;
vga_en<=‘1’ when cnt_h>=(128+88) and cnt_h<(128+88+800) and cnt_v>=(4+23) and cnt_v<(4+23+600) else’0’;
end a;
library ieee;
use ieee.std_logic_1164.all;
entity ps2led is
port(
RST_n : in std_logic;
CLK : in std_logic;
ps2clk : in std_logic;
ps2dat : in std_logic;
LED : out std_logic_vector(3 downto 0)
);
end ps2led;
architecture a of ps2led is
component ps2scan is
port(
rst_n : in std_logic;
clk : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_byte : out std_logic_vector(7 downto 0);
ps2_flag : out std_logic
);
end component;
signal ps2_flag : std_logic;
signal ps2_byte : std_logic_vector(7 downto 0);
signal ps2_flag_1, ps2_flag_2 : std_logic;
begin
U1 : ps2scan
port map(
rst_n => RST_n,
clk => CLK,
ps2_clk => ps2clk,
ps2_data => ps2dat,
ps2_byte => ps2_byte,
ps2_flag => ps2_flag
);
process(RST_n, CLK)
begin
if RST_n='0' then
LED <= "0000";
elsif CLK'event and CLK='1' then
if ps2_flag_2='0' and ps2_flag_1='1' then
case ps2_byte is
when x"1C" =>
LED<= "0001";
when x"1B" =>
LED <= "0010";
when x"23" =>
LED <= "0100";
when x"1D" =>
LED <= "1000";
when others =>
LED <= "0000";
end case;
end if;
end if;
end process;
process(RST_n, CLK)
begin
if RST_n='0' then
ps2_flag_1 <= '1';
ps2_flag_2 <= '1';
elsif CLK'event and CLK='1' then
ps2_flag_1 <= ps2_flag;
ps2_flag_2 <= ps2_flag_1;
end if;
end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
entity fds is
port( rst_n:in std_logic;
clk :in std_logic;
right_a:in std_logic;
left_a:in std_logic;
up_a:in std_logic;
down_a:in std_logic;
ps2clk : in std_logic;
ps2dat : in std_logic;
vga_h:out std_logic ;
vga_v:out std_logic ;
vga_r:out std_logic ;
vga_g:out std_logic ;
vga_b:out std_logic
);
end fds;
architecture a of fds is
component vga_drive is
port(
rst_n:in std_logic;
clk :in std_logic;
xpos:out integer ;
ypos: out integer ;
data:in std_logic_vector(2 downto 0);
vga_h:out std_logic ;
vga_v:out std_logic ;
vga_r:out std_logic ;
vga_g:out std_logic ;
vga_b:out std_logic
);
end component;
component vga_display is
port(rst_n:in std_logic ;
clk :in std_logic ;
right_a:in std_logic;
left_a:in std_logic;
up_a:in std_logic;
down_a:in std_logic;
xpos:in integer ;
ypos:in integer ;
LED : in std_logic_vector(3 downto 0);
data:out std_logic_vector(2 downto 0)
);
end component;
component ps2led is
port( RST_n : in std_logic;
CLK : in std_logic;
ps2clk : in std_logic;
ps2dat : in std_logic;
LED : out std_logic_vector(3 downto 0)
);
end component;
signal xpos:integer;
signal ypos:integer;
signal data:std_logic_vector(2 downto 0);
signal LED:std_logic_vector(3 downto 0);
begin
u1:vga_drive
port map(
rst_n =>rst_n,
clk =>clk,
xpos=>xpos,
ypos=>ypos ,
data=>data,
vga_h=>vga_h ,
vga_v=>vga_v ,
vga_r=>vga_r ,
vga_g=>vga_g ,
vga_b=>vga_b
);
u2:ps2led
port map(
rst_n=> RST_n,
CLK=>CLK ,
ps2clk=>ps2clk,
ps2dat=>ps2dat,
LED=>LED
);
u3:vga_display
port map(
rst_n =>rst_n,
clk =>clk,
right_a=>right_a,
left_a=>left_a,
up_a=>up_a,
down_a=>down_a,
xpos=>xpos,
ypos=>ypos ,
LED=>LED,
data=>data
);
end a;
library ieee;
use ieee.std_logic_1164.all;
entity ps2scan is
port(
rst_n : in std_logic;
clk : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_byte : out std_logic_vector(7 downto 0);
ps2_flag : out std_logic -- rising edge indicates a key loose
);
end ps2scan;
architecture a of ps2scan is
signal byte_cnt : integer range 0 to 15;
signal temp_data : std_logic_vector(7 downto 0);
signal f0_code : std_logic;
signal ps2_clk_1,ps2_clk_2 : std_logic;
begin
process(rst_n, clk)
begin
if RST_n='0' then
ps2_clk_1 <= '0';
ps2_clk_2 <= '0';
elsif clk'event and clk='1' then
ps2_clk_1 <= ps2_clk;
ps2_clk_2 <= ps2_clk_1;
end if;
end process;
process(rst_n, clk)
begin
if rst_n='0' then
byte_cnt <= 0;
temp_data <= (others=>'0');
elsif clk'event and clk='1' then
if (ps2_clk_1='0' and ps2_clk_2='1') then
if byte_cnt=0 then
byte_cnt <= byte_cnt + 1;
elsif byte_cnt<9 then
byte_cnt <= byte_cnt + 1;
temp_data(7 downto 0) <= ps2_data & temp_data(7 downto 1);
elsif byte_cnt<10 then
byte_cnt <= byte_cnt + 1;
else
byte_cnt <= 0;
end if;
end if;
end if;
end process;
process(rst_n, clk)
begin
if (rst_n='0')then
f0_code <= '0';
ps2_byte <= x"00";
ps2_flag <= '0';
elsif (clk'event and clk='1')then
if byte_cnt=10 then
if temp_data=x"F0" then
f0_code <= '1';
elsif f0_code='1' then
f0_code <= '0';
ps2_byte <= temp_data;
ps2_flag <= '1';
else
ps2_flag <= '0';
end if;
end if;
end if;
end process;
end a;
此源码控制使用为A S键交替按下分针加一
此源码控制使用为D 空格键交替按下时针加一
标签：std,VHDL,clk,signal,vga,VGA,logic,integer,源代码 来源： https://blog.csdn.net/han23762376/article/details/118873180