目录

• 1、2-to-1 multiplexer
• 2、2-to-1 bus multiplexer
• 3、9-to-1 multiplexer
• 4、256-to-1 multiplexer
• 5、256-to-1 4 bit multiplexer
• 参考资料：https://hdlbits.01xz.net/

1、2-to-1 multiplexer

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input a, b, sel,
    output out ); 
	assign out = sel?b:a;
endmodule

2、2-to-1 bus multiplexer

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
	assign out = sel?b:a;
endmodule

3、9-to-1 multiplexer

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to ‘1’.

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*) begin
        case(sel) 
            4'b0000:out = a;
            4'b0001:out = b;
            4'b0010:out = c;
            4'b0011:out = d;
            4'b0100:out = e;
            4'b0101:out = f;
            4'b0110:out = g;
            4'b0111:out = h;
            4'b1000:out = i;
            default:out = 16'hffff;
        endcase
    end
endmodule

4、256-to-1 multiplexer

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
endmodule

5、256-to-1 4 bit multiplexer

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
assign out[3:0] = in[(sel4)+3 : sel4]; 错误
A[a : b]的含义理解为vectorA中选择位的范围，其中a和b只能是常数，而不能是变量。

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
endmodule

参考资料：https://hdlbits.01xz.net/

标签：Circuits,multiplexer,module,Combinational,input,bit,sel,Multiplexers,out
来源： https://blog.csdn.net/qq_42189799/article/details/118861657