2021-05-25

使用quartus prime软件设计四位乘法器（Verilog语言编写）。

整个设计分为三个模块，分别为分频模块，四位乘法器模块，译码器模块。

（1）分频模块：主要是将DE0-NAN0的板载时钟50MHZ分频得出1s和1ms的输出时钟。

module fen(clkin,rst,clkout_1s,clkout_1ms);
input clkin,rst;
output reg clkout_1s,clkout_1ms;
reg [31:0] cnt_1s,cnt_1ms;

//生成1ms的分频信号
always@ (posedge clkin or posedge rst)
if (rst)
  cnt_1ms <= 0;
else if (cnt_1ms==49999)//rst==0
       cnt_1ms <= 0;
	  else
		 cnt_1ms <= cnt_1ms + 1;
		 
always@ (posedge clkin or posedge rst)
if (rst)
  clkout_1ms <= 0;
else if (cnt_1ms<=24999)
		  clkout_1ms <= 0;
	  else
		  clkout_1ms <= 1;
		 
//生成1s的分频信号
always@ (posedge clkin or posedge rst)
if (rst)
  cnt_1s <= 0;
else if (cnt_1s==49999999)
		 cnt_1s <= 0;
	  else
		 cnt_1s <= cnt_1s + 1;
		 
always@ (posedge clkin or posedge rst)
if (rst)
  clkout_1s <= 0;
else if (cnt_1s<=24999999)
		  clkout_1s <= 0;
	  else
		  clkout_1s <= 1;
endmodule

（2）四位乘法器模块：乘数ain和乘数bin相乘

module multer4(clk,rst,ain,bin,,result_D,result_H,result_L);
input clk,rst;
input [3:0] ain;
input [5:0] bin;

output [4:0] result_D,result_H,result_L;
 reg [9:0] result;
always @ (posedge clk or posedge rst)
 if (rst)
  begin
   result <= 0;
  end
 else
  begin
   result <= ain*bin;
	end


assign result_D=result/100;
assign result_H=result/10%10;
assign result_L=result%10;
endmodule

（3）译码器模块：相乘的结果由7段数码管显示出来，更直观的得到现象。

module decoder(clkout_1ms,An,rst,seg,result_D,result_H,result_L);
input clkout_1ms,rst;
input [4:0] result_D,result_H,result_L;
reg [9:0]out;
reg [1:0] counter_clkout;
output reg [0:3] An;
output reg [0:7] seg;


wire [3:0] Q_4;
wire [3:0] Q_3;
wire [3:0] Q_2;
wire [3:0] Q_1;




always @ (posedge clkout_1ms or posedge rst)
if (rst==1)
  counter_clkout <= 0;
  else if (counter_clkout ==3)
      counter_clkout <= 0;
else counter_clkout  <= counter_clkout+1 ;

 always @(counter_clkout)
 if(rst==1)
   An <=4'b0000;
 else
  begin
  case (counter_clkout)
3:begin An <= 4'b0111;
         out<=Q_4;end
2:begin An <= 4'b1011;
         out<=Q_3;end
1:begin An <= 4'b1101;
         out<=Q_2;end
0:begin An <= 4'b1110;
         out<=Q_1;end
default : An <= 4'b1111;
 endcase
 end
 
 always @(out)
  if(rst==1)
  seg = 8'b11111100;
 else
 begin
 case(out)
      0:seg = 8'b11111100;
		1:seg = 8'b01100000;
		2:seg = 8'b11011010;
		3:seg = 8'b11110010;
		4:seg = 8'b01100110;
		5:seg = 8'b10110110;
		6:seg = 8'b10111110;
		7:seg = 8'b11100000;
		8:seg = 8'b11111110;
		9:seg = 8'b11110110;
 default : seg = 8'b11111100;
 endcase
 end
 
assign Q_4 = 0;
assign Q_3 = result_D;
assign Q_2 = result_H;
assign Q_1 = result_L;
endmodule

标签：25,clkout,05,1ms,result,posedge,rst,reg,2021
来源： https://blog.csdn.net/m0_57758146/article/details/117265951