Verilog三段式状态机流水灯

FPGA学习笔记0： 三段式状态机流水灯
小白第一次写状态机，多有不足
参考：https://www.cnblogs.com/luxiaolai/p/3424344.html

module flow_led_FSM(Clk,Rst_n,led);
//定义状态空间
	input Clk;
	input Rst_n;
	
	output reg [3:0] led;
	
	reg [3:0] c_state;
	reg [3:0] n_state;
	reg [19:0] Cnt;
	reg flag;
	
	localparam
		led_0 = 4'b0001,
		led_1 = 4'b0010,
		led_2 = 4'b0100,
		led_3 = 4'b1000;

always@(posedge Clk or negedge Rst_n)begin
		if(!Rst_n)
			Cnt <= 20'b0;
		else if(Cnt == 20'd999_999)begin  //20ms
			Cnt <= 20'd0;
			flag = ~flag;
			end
		else
			Cnt <= Cnt+1'b1;
	end
	
//状态跳转
always@(posedge flag or negedge Rst_n)begin
	if(!Rst_n)
		c_state <= led_0;
	else
		c_state <= n_state;
end 

//下个状态判断
always@(*)begin
	n_state = led_0;
	case(c_state)
	  led_0:begin if(Rst_n) n_state<=led_1;else n_state<=led_0;end
     led_1:begin if(Rst_n) n_state<=led_2;else n_state<=led_0;end
     led_2:begin if(Rst_n) n_state<=led_3;else n_state<=led_0;end
     led_3:begin if(Rst_n) n_state<=led_0;else n_state<=led_0;end
     default: n_state<=led_0;	
	endcase
end

//各个状态下的动作
always@(c_state)begin
		case(c_state)
			led_0:led <= 4'b1110;
			led_1:led <= 4'b1101;
			led_2:led <= 4'b1011;
			led_3:led <= 4'b0111;
			default:led <= 4'b1110;
		endcase
end

endmodule 

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标签：----------------------------------------,led,三段式,Clk,状态机,Verilog,Rst,reg
来源： https://blog.csdn.net/chopess/article/details/114681191