EDA与VHDL题目——数字钟
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EDA与VHDL题目——数字钟
代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port (
clk : in std_logic;
reset : in std_logic;
reset2 : in std_logic;
xianshi : out std_logic_vector(7 downto 0); --
xuanze : out std_logic_vector(5 downto 0) --选择数码管亮灭
);
end clock;
architecture code1 of clock is
signal clk1: std_logic; -- 定义 1HZ 信号 秒表输入
signal clk2: std_logic; -- 定义 1/60 hz 信号 秒表输出，分钟输入
signal clk3: std_logic; --定义 1/3600 hz 信号 分钟输出，时钟输入
signal clk4: std_logic; --定义 1Khz 信号 用于 数码管选择
signal sh: std_logic_vector(3 downto 0):="0000";--秒个位
signal sl: std_logic_vector(3 downto 0):="0000";--秒十位
signal mh: std_logic_vector(3 downto 0):="0000";--分个位
signal ml: std_logic_vector(3 downto 0):="0000";--分十位
signal hl:std_logic_vector(3 downto 0):="0000";--时个位
signal hh:std_logic_vector(3 downto 0):="0000";--时十位
signal sel:std_logic_vector(2 downto 0);
signal A: std_logic_vector(3 downto 0);
begin
p1 :process (clk) --并行处理，进程1产生1Hz的信号clk1，作为秒表输入
variable count: integer range 0 to 25000000 := 0;
variable count1: std_logic := '1';
begin
if (clk'event and clk='1') then
count := count+1;
if count=25000000 then
count:=0;
count1:=not count1;
end if;
clk1 <= count1;
end if;
end process;
p2 :process (clk) --进程2 产生 1KHz 的信号clk4，作为数码管选择
variable count: integer range 0 to 25000 := 0;
variable count1: std_logic := '1';
begin
if clk'event and clk='1' then
count := count+1;
if count=25000 then
count:=0;
count1:=not count1;
end if;
clk4 <= count1;
end if;
end process;
p3 :process(clk1,reset) --进程3 秒表 以 1hz的clk1为输入，以 clk2 为输出
begin
if(reset = '0') then --异步清零
sh <= "0000";
sl <= "0000";
elsif(clk1'event and clk1 ='1') then -- 模60开始
if (sh="0101" and sl="1001" ) then
clk2 <= '1';
sh <= "0000";
sl <= "0000";
else
clk2 <= '0';
if (sl = 9) then
sl <= "0000";
if (sh = 5) then
sh <= "0000";
else
sh<= sh + 1;
end if;
else
sl <= sl + 1;
end if;
end if;
end if;
end process;
p4 :process(clk2,reset) --进程4 分钟 以 clk2为输入，以 clk3 为输出
begin
if (mh="0101" and ml="1001" ) then
clk3 <= '1';
else
clk3 <= '0';
if(reset = '0') then --异步清零
mh <= "0000";
ml <= "0000";
elsif(clk2'event and clk2 ='1') then -- 模60开始
if (ml = 9) then
ml <= "0000";
if (mh = 5) then
mh <= "0000";
else
mh<= mh + 1;
end if;
else
ml <= ml + 1;
end if;
end if;
end if;
end process;
p5:process(clk3) --进程5 时钟 以 clk2为输入，以 clk3 为输出
begin
if(reset = '1') then
if(clk3'event and clk3='1')then
hl<=hl+1;
if(hl = 9) then
hl<="0000";
hh<=hh + 1;
end if;
if(hh=2 and hl = 3)then
hh<="0000";
hl<="0000";
end if;
end if;
else
null;
end if;
end process;
p6:process(clk4,sl,sh,ml,mh,hl,hh) -- 选数码管 以1Khz信号输入，
begin
if clk4'event and clk4='1' then --6个数码管，不断地从 0-5 循环,不断选择数码管 频率为1khz
sel<=sel+1;
if (sel = 5) then
sel <= "000";
end if;
end if;
case sel is
when "000" => xuanze <= "111110";A <= sl; --秒个位, 选择数码管
when "001" => xuanze <= "111101";A <= sh;
when "010" => xuanze <= "111011";A <= ml;
when "011" => xuanze <= "110111";A <= mh;
when "100" => xuanze <= "101111";A <= hl;
when "101" => xuanze <= "011111";A <= hh; --时十位
when others => null;
end case;
case A is
when "0000" => xianshi <= "00111111"; --数码管表示数字 0 译码
when "0001" => xianshi <= "00000110"; --1
when "0010" => xianshi <= "01011011"; --2
when "0011" => xianshi <= "01001111"; --3
when "0100" => xianshi <= "01100110"; --4
when "0101" => xianshi <= "01101101"; --5
when "0110" => xianshi <= "01111101"; --6
when "0111" => xianshi <= "00000111"; --7
when "1000" => xianshi <= "01111111"; --8
when "1001" => xianshi <= "01101111"; --9
when others => null;
end case;
end process;
end code1;
标签：std,EDA,VHDL,--,数字钟,signal,downto,xianshi,logic 来源： https://blog.csdn.net/Alexa_/article/details/113790012