FPGA的并行性
作者:互联网
1.Verilog中的并行设计
实例1:
1 //Design 2 `timescale 1ns / 1ps 3 module Design( 4 input i_clk, 5 input i_rst_n, 6 output[3:0] o_cnt1,o_cnt2 7 ); 8 reg[3:0] r_cnt1,r_cnt2; 9 always@(posedge i_clk)begin 10 if(!i_rst_n) r_cnt1<='b0; 11 else r_cnt1<=r_cnt1+1'b1; 12 end 13 always@(posedge i_clk)begin 14 if(!i_rst_n) r_cnt2<='b0; 15 else r_cnt2<=r_cnt2+1'b1; 16 end 17 assign o_cnt1=r_cnt1; 18 assign o_cnt2=r_cnt2; 19 endmodule
1 TestBench 2 `timescale 1ns / 1ps 3 module TestBench(); 4 reg clk; 5 reg rst; 6 reg[3:0] i_cnt; 7 wire[3:0] o_cnt1,o_cnt2; 8 always#10 clk=!clk; 9 initial begin 10 clk<=0; 11 rst<=0; 12 #10 rst<=1; 13 end 14 Design my_design( 15 .i_clk(clk), 16 .i_rst_n(rst), 17 .o_cnt1(o_cnt1), 18 .o_cnt2(o_cnt2) 19 ); 20 endmodule
实例2:
Design
1 `timescale 1ns / 1ps 2 module Design( 3 input i_clk, 4 input i_rst_n, 5 input[3:0] i_cnt, 6 output[3:0] o_cnt1,o_cnt2 7 ); 8 reg[3:0] r_cnt1,r_cnt2; 9 always @(posedge i_clk) 10 if(!i_rst_n) begin 11 r_cnt1 <= 'b0; 12 r_cnt2 <= 'b0; 13 end 14 else begin 15 r_cnt1 <= i_cnt; 16 r_cnt2 <= i_cnt; 17 end 18 assign o_cnt1 = r_cnt1; 19 assign o_cnt2 = r_cnt2; 20 endmodule
TestBench
1 `timescale 1ns / 1ps 2 3 module TestBench(); 4 `define CLK_PERIORD 10 //时钟周期设置为10ns(100MHz) 5 6 //接口申明 7 reg clk; 8 reg rst_n; 9 reg[3:0] i_cnt; 10 wire[3:0] o_cnt1,o_cnt2; 11 12 //对被测试的设计进行例化 13 Design uut_vlg_design_ex2( 14 .i_clk(clk), 15 .i_rst_n(rst_n), 16 .i_cnt(i_cnt), 17 .o_cnt1(o_cnt1), 18 .o_cnt2(o_cnt2) 19 ); 20 21 //复位和时钟产生 22 //时钟和复位初始化、复位产生 23 initial begin 24 clk <= 0; 25 rst_n <= 0; 26 i_cnt <= 0; 27 #10; 28 rst_n <= 1; 29 @(posedge clk); #2; 30 i_cnt <= 4'd1; 31 @(posedge clk); #2; 32 i_cnt <= 4'd2; 33 @(posedge clk); #2; 34 i_cnt <= 4'd3; 35 @(posedge clk); #2; 36 i_cnt <= 4'd4; 37 end 38 //时钟产生 39 always #(`CLK_PERIORD/2) clk = ~clk; 40 41 //测试激励产生 42 initial begin 43 @(posedge rst_n); //等待复位完成 44 @(posedge clk); 45 repeat(300) begin 46 @(posedge clk); 47 end 48 $stop; 49 end 50 endmodule
标签:10,FPGA,clk,并行性,cnt2,cnt1,rst,reg 来源: https://www.cnblogs.com/Leeyoung888/p/13974688.html