[SV]SystemVerilog Randomization
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SystemVerilog Randomization
一、OOP Based Randomization
1、Two types of random properties are supported:
-
rand
-
randc
2、randand randcproperties are randomized when the class method randomize()is called:
-
Randomize property value to full range of data type
-
randomize()is built-in with every class
-
1 is returned if successful, 0 if randomization failed
3、randproperties can assume any legal value:
-
Values can repeat without exhausting all possible values
4、randcproperties can be up to 16 bits:
-
Exhaust all values before repeating any individual value
-
For non-repeating bit values > 16 bits, use concatenation
二、Implication and Order Constraints
1、Implication operators:
- ->
- if ( … ) … [ else … ]
- Caution: does not imply solving order
typedef enum { low, mid, high } AddrType;
class MyBus;
rand bit[7:0] addr;
rand AddrType atype;
constraint addr_range {
(atype == low ) ->addr inside { [0:15] };
(atype == mid ) ->addr inside { [16:127] };
(atype == high) ->addr inside { [128:255] };
// same as:
// if(atype == low) addr inside { [0:15] };
// if(atype == mid) addr inside { [16:127] };
// if(atype == high) addr inside { [128:255] };
}
endclass
2、Dictating solver order
- randcis solved before randproperties
- solve-beforeconstruct set solving order for same type random properties
- Can not force randto be randomized before randcproperties
- $void(rand_property)solves rand_propertiesfirst
class MyBus;
rand bit flag;
rand int addr;
constraint addr_range {
if ( flag == 0 ) addr == 0;
else addr inside { [1:1024] };
solveflag beforeaddr;
// solve addr before flag; // what’s the difference?
// alternative:
// if ( $void(flag) == 0 ) addr == 0;
}
endclass
三、Effects of Calling randomize()
1、When randomize()executes, three events occur
- pre_randomize()is called
- Randomization is executed
- post_randomize()is called
2、pre_randomize()
- Optional
- Set/Correct constraints before randomization
3、post_randomize()
- Optional
- Make corrections after randomization
- Example: CRC
class Packet;
int test_mode;
rand bit[3:0] sa, da;
rand bit[7:0] payload[];
bit[15:0] crc;
constraint LimitA {
sa inside { [0:7] };
da inside { [0:7] };
payload.size() inside { [2:4] };
}
function void pre_randomize();
if(test_mode) recnstr(test_mode)
endfunction
function void post_randomize();
gen_crc();
endfunction
virtual function void recnstr(int mode);
endtask
endclass
4、Inline Constraints
- syntax: obj.randomize( ) with{ <new constraints> };
5、Controlling randProperty Randomization
- task/function int object_name.property.rand_mode ( 0 | 1 );
program automatic test;
class Node;
rand int x, y, z;
constraint Limit1 {
x inside {[0:16]}; y inside {[23:41]};
z < y; z > x;
}
endclass
initial begin
Node obj1 = new();
obj1.x.rand_mode(0);
if (!obj1.randomize()) ...;
end
endprogram
标签:rand,addr,inside,atype,SV,Randomization,bit,randomize,SystemVerilog 来源: https://blog.csdn.net/gsjthxy/article/details/105341253