CSE 410 Spring 2019 Computer Project

CSE 410 Spring 2019
Computer Project #7
Assignment Overview
This assignment focuses on the interactions between primary storage and the data cache, and is the first milestone
in a larger simulation. You will design and implement the C/C++ program which is described below.
It is worth 30 points (3% of course grade) and must be completed no later than 11:59 PM on Thursday, 3/21.
Assignment Deliverables
The deliverables for this assignment are the following files:
proj07.makefile – the makefile which produces proj07
proj07.student.c – the source code file for your solution
Be sure to use the specified file names and to submit your files for grading via the CSE Handin system before the
project deadline.
Assignment Specifications
The program will simulate the steps required to manage primary storage and the data cache. Primary storage
consists of 65,536 bytes of RAM; physical addresses are 16 bits in length. The data cache is a direct-mapped,
write-back cache which contains 8 lines. Each cache line contains 16 bytes of data, as well as the control
information (valid bit, modified bit, and tag bits).
1. Your program will accept command-line arguments to specify the file which contains the initial contents of RAM
(the "-ram" option), the file which contains the memory references (the "-refs" option), and to control the display
of debugging information (the "-debug" option).
2. The "-ram" option will be followed by the name of the file which contains the initial contents of RAM. The first
line of that file will contain a hexadecimal address (four hexadecimal digits, with leading zeroes); that address will
be a multiple of 16. That line will be followed by zero or more lines, each of which contains 16 bytes of data (two
hexadecimal digits, with leading zeroes). For example:
0ac0
28 ab 18 c3 4c ff 9e 51 b4 82 59 7a b3 74 01 ef
9d e3 bf a0 31 00 00 86 b0 16 21 d4 e0 06 00 00
11 00 00 43 90 12 21 1e 92 10 00 11 40 00 43 03
Your program will copy those bytes into RAM, starting at the specified address. All unspecified RAM addresses will
contain the value zero.
3. The "-refs" option will be followed by the name of the file which contains zero or more memory references.
Each line of the file will contain the following information:
a) physical address being referenced (four hexadecimal digits, with leading zeroes)
b) operation being performed (one character; ‘R’ for read and ‘W’ for write)
c) if the operation is a write, the value being written (four bytes, where each byte is given as two
hexadecimal digits, with leading zeroes)
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:
0bd8 R
0ac4 W 12 34 56 78
0ad0 R
4. For each memory reference in the file, your program will display one line with the following information:
a) physical address being referenced (four hexadecimal digits, with leading zeroes)
b) operation being performed (one character; ‘R’ for read and ‘W’ for write)
c) cache line accessed (one hexadecimal digit)
d) tag bits (three hexadecimal digits, with leading zeroes)
e) byte offset (one hexadecimal digit)
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:
0bd8 R 5 017 8
0ac4 W 4 015 4
0ad0 R 5 015 0
5. After the simulation is completed, your program will display the current contents of the subset of RAM which
was initialized from the input file. Each line of that display will include an address (four hexadecimal digits, with
leading zeroes) and the 16 bytes of data starting at that address (two hexadecimal digits, with leading zeroes).
Items in the line will be separated by exactly one space, and the line will terminate with a newline. The display will
begin and end with a blank line (for readability). For example:
0ac0 11 22 33 44 4c ff 9e 51 b4 82 59 7a b3 74 01 ef
0ad0 9d e3 bf a0 31 00 00 86 b0 16 21 d4 55 66 77 88
0ae0 11 00 00 43 99 aa bb cc 92 10 00 11 40 00 43 03
6. After the simulation is completed, your program will display the contents of the data cache. The display will
contain one line for each data cache entry:
a) index of the data cache entry (one hexadecimal digit)
b) V bit (one character; ‘0’ for not valid, ‘1’ for valid)
c) M bit (one character; ‘0’ for not modified, ‘1’ for modified)
d) tag bits (three hexadecimal digits, with leading zeroes)
e) data block (16 bytes of data, where each byte is given as two hexadecimal digits, with leading zeroes)
Items within a line will be separated by exactly one space, and each line will terminate with a newline. The data
cache display will begin and end with a blank line (for readability), and will include appropriate column headers.
7. If the "-debug" option has been selected, your program will display:
a) the contents of the subset of RAM at the start of the simulation
b) the contents of the data cache at the start of the simulation
c) the contents of the data cache after each memory reference is processed
8. The program will include appropriate error-handling.
Assignment Notes
1. As stated above, your source code file will be named "proj07.student.c"; that source code file may contain C or
C++ statements.
2. You must use "g++" to translate your source code file in the CSE Linux environment.
3. Valid executions of the program might appear as follows:
proj07 -ram ram_file -refs ref_file -debug
proj07 –refs fileA –ram fileB
proj07 –debug –refs test1
proj07 –refs test2
4. Your program must create a data structure representing the data cache and set all of the entries to zero at the
start of the simulation.
For this assignment, processing the memory references will not update the data cache. In subsequent
assignments, your program will actively manage the data cache (and thus the display will change over time).
5. Your program must create a data structure representing the RAM and set all of the entries to zero at the start of
the simulation. If the "-ram" option is selected, a subset of the RAM will be initialized using the contents of the
specified file.
For this assignment, processing the memory references will not update the RAM. In subsequent assignments, your
program will actively manage the RAM (and thus the display will change over time).

代做CSE 410作业、C/C++程序作业调试、代写C/C++语言作业、代做CSE Handin作业
CSE 410 Spring 2019
Computer Project #7
Assignment Overview
This assignment focuses on the interactions between primary storage and the data cache, and is the first milestone
in a larger simulation. You will design and implement the C/C++ program which is described below.
It is worth 30 points (3% of course grade) and must be completed no later than 11:59 PM on Thursday, 3/21.
Assignment Deliverables
The deliverables for this assignment are the following files:
proj07.makefile – the makefile which produces proj07
proj07.student.c – the source code file for your solution
Be sure to use the specified file names and to submit your files for grading via the CSE Handin system before the
project deadline.
Assignment Specifications
The program will simulate the steps required to manage primary storage and the data cache. Primary storage
consists of 65,536 bytes of RAM; physical addresses are 16 bits in length. The data cache is a direct-mapped,
write-back cache which contains 8 lines. Each cache line contains 16 bytes of data, as well as the control
information (valid bit, modified bit, and tag bits).
1. Your program will accept command-line arguments to specify the file which contains the initial contents of RAM
(the "-ram" option), the file which contains the memory references (the "-refs" option), and to control the display
of debugging information (the "-debug" option).
2. The "-ram" option will be followed by the name of the file which contains the initial contents of RAM. The first
line of that file will contain a hexadecimal address (four hexadecimal digits, with leading zeroes); that address will
be a multiple of 16. That line will be followed by zero or more lines, each of which contains 16 bytes of data (two
hexadecimal digits, with leading zeroes). For example:
0ac0
28 ab 18 c3 4c ff 9e 51 b4 82 59 7a b3 74 01 ef
9d e3 bf a0 31 00 00 86 b0 16 21 d4 e0 06 00 00
11 00 00 43 90 12 21 1e 92 10 00 11 40 00 43 03
Your program will copy those bytes into RAM, starting at the specified address. All unspecified RAM addresses will
contain the value zero.
3. The "-refs" option will be followed by the name of the file which contains zero or more memory references.
Each line of the file will contain the following information:
a) physical address being referenced (four hexadecimal digits, with leading zeroes)
b) operation being performed (one character; ‘R’ for read and ‘W’ for write)
c) if the operation is a write, the value being written (four bytes, where each byte is given as two
hexadecimal digits, with leading zeroes)
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:
0bd8 R
0ac4 W 12 34 56 78
0ad0 R
4. For each memory reference in the file, your program will display one line with the following information:
a) physical address being referenced (four hexadecimal digits, with leading zeroes)
b) operation being performed (one character; ‘R’ for read and ‘W’ for write)
c) cache line accessed (one hexadecimal digit)
d) tag bits (three hexadecimal digits, with leading zeroes)
e) byte offset (one hexadecimal digit)
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:
0bd8 R 5 017 8
0ac4 W 4 015 4
0ad0 R 5 015 0
5. After the simulation is completed, your program will display the current contents of the subset of RAM which
was initialized from the input file. Each line of that display will include an address (four hexadecimal digits, with
leading zeroes) and the 16 bytes of data starting at that address (two hexadecimal digits, with leading zeroes).
Items in the line will be separated by exactly one space, and the line will terminate with a newline. The display will
begin and end with a blank line (for readability). For example:
0ac0 11 22 33 44 4c ff 9e 51 b4 82 59 7a b3 74 01 ef
0ad0 9d e3 bf a0 31 00 00 86 b0 16 21 d4 55 66 77 88
0ae0 11 00 00 43 99 aa bb cc 92 10 00 11 40 00 43 03
6. After the simulation is completed, your program will display the contents of the data cache. The display will
contain one line for each data cache entry:
a) index of the data cache entry (one hexadecimal digit)
b) V bit (one character; ‘0’ for not valid, ‘1’ for valid)
c) M bit (one character; ‘0’ for not modified, ‘1’ for modified)
d) tag bits (three hexadecimal digits, with leading zeroes)
e) data block (16 bytes of data, where each byte is given as two hexadecimal digits, with leading zeroes)
Items within a line will be separated by exactly one space, and each line will terminate with a newline. The data
cache display will begin and end with a blank line (for readability), and will include appropriate column headers.
7. If the "-debug" option has been selected, your program will display:
a) the contents of the subset of RAM at the start of the simulation
b) the contents of the data cache at the start of the simulation
c) the contents of the data cache after each memory reference is processed
8. The program will include appropriate error-handling.
Assignment Notes
1. As stated above, your source code file will be named "proj07.student.c"; that source code file may contain C or
C++ statements.
2. You must use "g++" to translate your source code file in the CSE Linux environment.
3. Valid executions of the program might appear as follows:
proj07 -ram ram_file -refs ref_file -debug
proj07 –refs fileA –ram fileB
proj07 –debug –refs test1
proj07 –refs test2
4. Your program must create a data structure representing the data cache and set all of the entries to zero at the
start of the simulation.
For this assignment, processing the memory references will not update the data cache. In subsequent
assignments, your program will actively manage the data cache (and thus the display will change over time).
5. Your program must create a data structure representing the RAM and set all of the entries to zero at the start of
the simulation. If the "-ram" option is selected, a subset of the RAM will be initialized using the contents of the
specified file.
For this assignment, processing the memory references will not update the RAM. In subsequent assignments, your
program will actively manage the RAM (and thus the display will change over time).

代做CSE 410作业、C/C++程序作业调试、代写C/C++语言作业、代做CSE Handin作业
CSE 410 Spring 2019
Computer Project #7
Assignment Overview
This assignment focuses on the interactions between primary storage and the data cache, and is the first milestone
in a larger simulation. You will design and implement the C/C++ program which is described below.
It is worth 30 points (3% of course grade) and must be completed no later than 11:59 PM on Thursday, 3/21.
Assignment Deliverables
The deliverables for this assignment are the following files:
proj07.makefile – the makefile which produces proj07
proj07.student.c – the source code file for your solution
Be sure to use the specified file names and to submit your files for grading via the CSE Handin system before the
project deadline.
Assignment Specifications
The program will simulate the steps required to manage primary storage and the data cache. Primary storage
consists of 65,536 bytes of RAM; physical addresses are 16 bits in length. The data cache is a direct-mapped,
write-back cache which contains 8 lines. Each cache line contains 16 bytes of data, as well as the control
information (valid bit, modified bit, and tag bits).
1. Your program will accept command-line arguments to specify the file which contains the initial contents of RAM
(the "-ram" option), the file which contains the memory references (the "-refs" option), and to control the display
of debugging information (the "-debug" option).
2. The "-ram" option will be followed by the name of the file which contains the initial contents of RAM. The first
line of that file will contain a hexadecimal address (four hexadecimal digits, with leading zeroes); that address will
be a multiple of 16. That line will be followed by zero or more lines, each of which contains 16 bytes of data (two
hexadecimal digits, with leading zeroes). For example:
0ac0
28 ab 18 c3 4c ff 9e 51 b4 82 59 7a b3 74 01 ef
9d e3 bf a0 31 00 00 86 b0 16 21 d4 e0 06 00 00
11 00 00 43 90 12 21 1e 92 10 00 11 40 00 43 03
Your program will copy those bytes into RAM, starting at the specified address. All unspecified RAM addresses will
contain the value zero.
3. The "-refs" option will be followed by the name of the file which contains zero or more memory references.
Each line of the file will contain the following information:
a) physical address being referenced (four hexadecimal digits, with leading zeroes)
b) operation being performed (one character; ‘R’ for read and ‘W’ for write)
c) if the operation is a write, the value being written (four bytes, where each byte is given as two
hexadecimal digits, with leading zeroes)
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:
0bd8 R
0ac4 W 12 34 56 78
0ad0 R
4. For each memory reference in the file, your program will display one line with the following information:
a) physical address being referenced (four hexadecimal digits, with leading zeroes)
b) operation being performed (one character; ‘R’ for read and ‘W’ for write)
c) cache line accessed (one hexadecimal digit)
d) tag bits (three hexadecimal digits, with leading zeroes)
e) byte offset (one hexadecimal digit)
Items in the line will be separated by exactly one space, and the line will terminate with a newline. For example:
0bd8 R 5 017 8
0ac4 W 4 015 4
0ad0 R 5 015 0
5. After the simulation is completed, your program will display the current contents of the subset of RAM which
was initialized from the input file. Each line of that display will include an address (four hexadecimal digits, with
leading zeroes) and the 16 bytes of data starting at that address (two hexadecimal digits, with leading zeroes).
Items in the line will be separated by exactly one space, and the line will terminate with a newline. The display will
begin and end with a blank line (for readability). For example:
0ac0 11 22 33 44 4c ff 9e 51 b4 82 59 7a b3 74 01 ef
0ad0 9d e3 bf a0 31 00 00 86 b0 16 21 d4 55 66 77 88
0ae0 11 00 00 43 99 aa bb cc 92 10 00 11 40 00 43 03
6. After the simulation is completed, your program will display the contents of the data cache. The display will
contain one line for each data cache entry:
a) index of the data cache entry (one hexadecimal digit)
b) V bit (one character; ‘0’ for not valid, ‘1’ for valid)
c) M bit (one character; ‘0’ for not modified, ‘1’ for modified)
d) tag bits (three hexadecimal digits, with leading zeroes)
e) data block (16 bytes of data, where each byte is given as two hexadecimal digits, with leading zeroes)
Items within a line will be separated by exactly one space, and each line will terminate with a newline. The data
cache display will begin and end with a blank line (for readability), and will include appropriate column headers.
7. If the "-debug" option has been selected, your program will display:
a) the contents of the subset of RAM at the start of the simulation
b) the contents of the data cache at the start of the simulation
c) the contents of the data cache after each memory reference is processed
8. The program will include appropriate error-handling.
Assignment Notes
1. As stated above, your source code file will be named "proj07.student.c"; that source code file may contain C or
C++ statements.
2. You must use "g++" to translate your source code file in the CSE Linux environment.
3. Valid executions of the program might appear as follows:
proj07 -ram ram_file -refs ref_file -debug
proj07 –refs fileA –ram fileB
proj07 –debug –refs test1
proj07 –refs test2
4. Your program must create a data structure representing the data cache and set all of the entries to zero at the
start of the simulation.
For this assignment, processing the memory references will not update the data cache. In subsequent
assignments, your program will actively manage the data cache (and thus the display will change over time).
5. Your program must create a data structure representing the RAM and set all of the entries to zero at the start of
the simulation. If the "-ram" option is selected, a subset of the RAM will be initialized using the contents of the
specified file.
For this assignment, processing the memory references will not update the RAM. In subsequent assignments, your
program will actively manage the RAM (and thus the display will change over time).

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