HDL Bits---More Verilog Features

2.5.1 Conditional temary operator 

module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
wire [7:0]r1,r2;  //记得定义位宽
assign r1=(a<b)?a:b;
assign r2=(c<d)?c:d;
assign min=(r1<r2)?r1:r2;
endmodule

2.5.2 Reduction operator

略

2.5.3 Reduction: Even wider gates(gates 100)

略

2.5.4 Combinational for-loop :vector reversal 2

把给定100位输入向量的位序翻转并输出

module top_module(
input [99:0] in,
output [99:0] out
);
integer i;
always@(*)
begin
for(i=0;i<100;i=i+1)
out[i]=in[99-i];
end
endmodule

2.5.5 Combinational for-loop:255-bit population count

module top_module(

input [254:0] in,
output [7:0] out );
int i;       
always@(*)
begin
out=0;     //初始值定义
for(i=0;i<255;i=i+1)
out=out+in[i];
end
endmodule

2.5.6 Generate for-loop:100-bit binary adder2

实例化100个全加器来构建一个100位纹波进位加法器。加法器将2个100位输入与低位的进位相加，以产生100位和以及进位

module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
full_adder adder_0(a[0],b[0],cin,cout[0],sum[0]);      //cout,sum顺序要注意

generate
genvar i;
for(i=1;i<100;i=i+1)begin:full_adder
full_adder adder_i(a[i],b[i],cout[i-1],cout[i],sum[i]);
end
endgenerate
endmodule


module full_adder(
input a,b,
input cin,
output cout,sum);
assign {cout,sum}=a+b+cin;
endmodule

2.5.7 Generate for-loop:100-digit BCD adder

module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire [99:0]cout0;
bcd_fadd fadd_0(a[3:0],b[3:0],cin,cout0[0],sum[3:0]);
generate
genvar i;
for(i=1;i<100;i=i+1)begin:bcd
bcd_fadd fadd_i(a[(4*i+3):(4*i)],b[(4*i+3):(4*i)],cout0[i-1],cout0[i],sum[(4*i+3):(4*i)]);
end
endgenerate
assign cout=cout0[99];
endmodule

标签：99,cout,sum,module,---,Verilog,input,100,Features
来源： https://www.cnblogs.com/luckyu922/p/16444383.html