Bulid a circuits from simulation waveform
作者:互联网
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input a,
input b,
output q );//
assign q = a&b; // Fix me
endmodule
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q=~a&~b&~c&~d|~a&~b&c&d|~a&b&~c&d|~a&b&c&~d|a&~b&~c&d|a&~b&c&~d|a&b&~c&~d|a&b&c&d; // Fix me
endmodule
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q=b&d|b&c|a&d|a&c; // Fix me
endmodule
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q=b|c; // Fix me
endmodule
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
多路选择器,c选择。
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
always @(*) begin
case(c)
4'd0:q<=b;
4'd1:q<=e;
4'd2:q<=a;
4'd3:q<=d;
default:q<=4'hf;
endcase
end
endmodule
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input [2:0] a,
output [15:0] q );
always @(*) begin
case(a)
3'd0:q<=16'h1232;
3'd1:q<=16'haee0;
3'd2:q<=16'h27d4;
3'd3:q<=16'h5a0e;
3'd4:q<=16'h2066;
3'd5:q<=16'h64ce;
3'd6:q<=16'hc526;
default:q<=16'h2f19;
endcase
end
endmodule
This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input clk,
input a,
output q );
always @(posedge clk) begin
q<=~a;
end
endmodule
This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it
p为a在clock为高电平时的选通信号,q为clock下降沿触发的信号,存放p的值。
module top_module (
input clock,
input a,
output p,
output q );
assign p=clock?a:p;
always @(negedge clock) begin
q<=p;
end
endmodule
This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input clk,
input a,
output [3:0] q );
always @(posedge clk) begin
if(a)
q<=4'd4;
else if(q==4'd6)
q<=4'd0;
else if(!a)
q<=q+1'd1;
else
q<=q;
end
endmodule
This is a sequential circuit. The circuit consists of combinational logic and one bit of memory (i.e., one flip-flop). The output of the flip-flop has been made observable through the output state.
Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input clk,
input a,
input b,
output q,
output state );
always @(posedge clk) begin
if(a&b)
state<=1'b1;
else if(~a&~b)
state<=1'b0;
else
state<=state;
end
assign q=a^b^state;
endmodule
标签:Bulid,waveforms,circuits,module,simulation,waveform,circuit,output,input 来源: https://blog.csdn.net/yl2021/article/details/123180833