阶段3-练习2

数din_vld 连续 持续10个时钟 ，中间有间断后，又重新开始计数，直到数到连续持续10个时钟时，才将din赋给dout，即使连续持续满了10个时钟之后，din也不会在赋给dout，只在第一个连续持续满10个时钟的那一刻才将din赋给dout

 1 module cnt_test(
 2                 clk,
 3                 rst_n,
 4                 din_vld,
 5                 din,
 6                 dout
 7 );
 8 
 9 input     clk;
10 input     rst_n;
11 input      din_vld;
12 
13 input      [3:0] din;
14 
15 output     [3:0] dout;
16 reg     [3:0] dout;
17 reg     [3:0] cnt0;
18 
19 reg  flag_add;
20 wire add_cnt0;
21 wire end_cnt0;
22 
23 always @(posedge clk or negedge rst_n)begin
24     if(!rst_n)begin
25         cnt0 <= 0;
26     end
27     else if(add_cnt0)begin
28         if(end_cnt0)
29             cnt0 <= 0;
30         else
31             cnt0 <= cnt0 + 1;
32     end
33     else begin  //记得清零，方便下次开始计数，比如刚开始计数到2个时,din_vld拉低了，这个时候计数器cnt0要清零，方便下次开始重新计数
34         cnt0 <= 0;
35     end
36 end
37 
38 //因为计数器到10之后，din_vld可能还是高电平，不加flag_add判断条件，那么计数器就会一直计数，cnt0可能就一直增加到10然后又变为0开始，结果就完全不对了    
39 assign add_cnt0 = din_vld && flag_add == 0 ; //引入flag_add 信号，是为了区分计数器满了之后的前后
40 assign end_cnt0 = add_cnt0 && cnt0 == 10 -1 ;
41 
42 always @(posedge clk or negedge rst_n)begin
43     if(!rst_n)begin
44         flag_add <= 0;
45     end
46     else if(end_cnt0)begin
47         flag_add <= 1;
48     end
49     else if(din_vld == 0)begin //当din_vld变0时，flag_add就赋0，比如刚开始计数到2个时,din_vld拉低了，就要停止计数，且计数器cnt0也要清零，方便下次计数
50         flag_add <= 0;
51     end
52 end
53 
54 always @(posedge clk or negedge rst_n)begin
55     if(!rst_n)begin
56         dout <= 0;
57     end
58     else if(end_cnt0)begin
59         dout <= din;
60     end
61 end
62 
63 endmodule

测试激励代码：

  1 module top_sim();
  2 
  3 reg         clk;
  4 reg         rst_n;
  5 reg         din_vld;
  6 reg [3:0]      din;
  7 
  8 wire [3:0] dout;
  9 
 10 parameter CLK_CYCLE    = 20;
 11 
 12 initial begin
 13     clk = 0;
 14     forever begin
 15         #(CLK_CYCLE/2);
 16         clk = ~clk;
 17     end
 18         
 19 end
 20 
 21 initial begin
 22     #1;
 23     rst_n = 0;
 24     #(CLK_CYCLE*2);
 25     rst_n = 1;
 26 end
 27 
 28 initial begin
 29     #1;
 30     din_vld = 0;
 31     repeat(2)begin
 32         #(10*CLK_CYCLE);
 33         din_vld = 1;
 34         #(2*CLK_CYCLE);
 35         din_vld = 0;
 36         #(2*CLK_CYCLE);
 37         din_vld = 1;
 38         #(12*CLK_CYCLE);
 39         din_vld = 0;
 40         #(5*CLK_CYCLE);
 41         din_vld = 1;
 42         #(13*CLK_CYCLE);
 43         din_vld = 0;
 44         #(2*CLK_CYCLE);
 45     end
 46 end
 47 
 48 initial begin
 49     #1;
 50     din <= 0;
 51     repeat(2)begin
 52         #(10*CLK_CYCLE);
 53         din <= 3;
 54         #(3*CLK_CYCLE);
 55         din <= 2;
 56         #(4*CLK_CYCLE);
 57         din <= 5;
 58         #(2*CLK_CYCLE);
 59         din <= 1;
 60         #(1*CLK_CYCLE);
 61         din <= 8;
 62         #(2*CLK_CYCLE);
 63         din <= 6;
 64         #(3*CLK_CYCLE);
 65         din <= 7;
 66         #(6*CLK_CYCLE);
 67         din <= 1;
 68         #(1*CLK_CYCLE);
 69         din <= 3;
 70         #(2*CLK_CYCLE);
 71         din <= 2;
 72         #(2*CLK_CYCLE);
 73         din <= 5;
 74         #(4*CLK_CYCLE);
 75         din <= 1;
 76         #(2*CLK_CYCLE);
 77         din <= 8;
 78         #(8*CLK_CYCLE);
 79         din <= 6;
 80         #(1*CLK_CYCLE);
 81         din <= 7;
 82         #(2*CLK_CYCLE);
 83         din <= 1;
 84         #(10*CLK_CYCLE);
 85         din <= 3;
 86         #(3*CLK_CYCLE);
 87         din <= 2;
 88         #(4*CLK_CYCLE);
 89         din <= 5;
 90         #(2*CLK_CYCLE);
 91         din <= 1;
 92         #(1*CLK_CYCLE);
 93         din <= 8;
 94         #(2*CLK_CYCLE);
 95         din <= 6;
 96         #(3*CLK_CYCLE);
 97         din <= 7;
 98         #(6*CLK_CYCLE);
 99         din <= 1;
100         #(1*CLK_CYCLE);
101         din <= 3;
102         #(2*CLK_CYCLE);
103         din <= 2;
104         #(2*CLK_CYCLE);
105         din <= 5;
106         #(4*CLK_CYCLE);
107         din <= 1;
108         #(2*CLK_CYCLE);
109         din <= 8;
110         #(8*CLK_CYCLE);
111         din <= 6;
112         #(1*CLK_CYCLE);
113         din <= 7;
114         #(2*CLK_CYCLE);
115         din <= 1;
116     end
117 end
118 
119 
120 cnt_test        u1(    
121                         .clk(clk),
122                         .rst_n(rst_n),
123                         .din_vld(din_vld),
124                         .din(din),
125                         .dout(dout)
126                         
127 );
128 
129 endmodule 

仿真波形：

 

标签：begin,din,CLK,clk,练习,vld,阶段,CYCLE
来源： https://www.cnblogs.com/wen2376/p/15933870.html