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The fastest Verilog/SystemVerilog simulator!

作者:互联网

Verilator is the fastest Verilog/SystemVerilog simulator.

Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code. The user writes a little C++/SystemC wrapper file, which instantiates the "Verilated" model of the user's top level module. These C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.

Verilator:

iverilog生成"汇编",vvp从汇编生成字节码,然后解释执行。On a single thread Verilator is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). 但是: Icarus is a full featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may.

我一直幻想的东西有人做了,我再幻想另一个: CLogic - Concise Logic,or China Logic. 先照抄Verilog的RTL (Register Transfer Level)部分,但是begin,end换{},endmodule换},然后模仿Chisel加功能。词法和语法分析用flex, bison或python的ply来做,CLogic编译器可以用python来写。CLogic编译器的输出是.v文件,然后再用Verilator/Icarus进一步处理。

可行性分析:

标签:simulator,Chisel,C++,simulators,Verilog,Icarus,Verilator,SystemVerilog,fastest
来源: https://www.cnblogs.com/funwithwords/p/15777525.html