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LIBRARY IEEE; --1位二进制全加器顶层设计描述
USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT (ain, bin, cin : IN STD_LOGIC; cout, sum : OUT STD_LOGIC); END ENTITY f_adder; ARCHITECTURE fd1 OF f_adder IS COMPONENT h_adder --调用半加器声明语句 PORT ( a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END COMPONENT; COMPONENT or2a PORT (a, b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT;SIGNAL d, e, f : STD_LOGIC; --定义3个信号作为内部的连接线 BEGIN u1 : h_adder PORT MAP(a=>ain, b=>bin, co=>d, so=>e); --例化语句 u2 : h_adder PORT MAP(a=>e, b=>cin, co=>f, so=>sum); u3 : or2a PORT MAP(a=>d, b=>f, c=>cout); END ARCHITECTURE fd1; LIBRARY IEEE; --半加器描述(1)：布尔方程描述方法USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT ( a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder; ARCHITECTURE fh1 OF h_adder IS BEGIN so <= NOT(a XOR (NOT b)) ; co <= a AND b ; END ARCHITECTURE fh1;LIBRARY IEEE ; --或门逻辑描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT (a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or2a ; ARCHITECTURE one OF or2a IS BEGIN c <= a OR b ; END ARCHITECTURE one ;

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来源： https://blog.csdn.net/weixin_54338061/article/details/121424458