HDLBits（5）----D latch

目录

• • 1. D latch
  • 2. Exams/m2014 q4d
  • 3. Exams/2014 q4a
  • 4. Exams/ece241 2014 q

1. D latch

Implement the following circuit:
Note that this is a latch, so a Quartus warning about having inferred a latch is expected.

module top_module (
    input d, 
    input ena,
    output q);
    
    always@(*)
        begin
            if(ena) q <= d;     
        end
endmodule

2. Exams/m2014 q4d

module top_module (
    input clk,
    input in, 
    output out);
    
    always@(posedge clk)
        begin
           out<= out ^in; 
        end

endmodule

3. Exams/2014 q4a

module top_module (
    input clk,
    input w, R, E, L,
    output reg Q
);
    wire mid_a;
    wire mid_b;
    assign mid_b = L ? R :mid_a;
    assign mid_a = E ? w :Q;
    always@(posedge clk)
        begin
            Q <= mid_b;
            
        end

endmodule

4. Exams/ece241 2014 q

module top_module (
    input clk,
    input x,
    output z
); 
    reg a,b,c;
    wire D_a,D_b,D_c;
    assign D_a = x ^a;
    assign D_b = x & (!b);
    assign D_c = x | (!c);
    assign z = !(a|b|c);
    always @(posedge clk)
        begin
           a <= D_a;
           b <= D_b;
            c <= D_c;
            
        end

endmodule

标签：clk,HDLBits,mid,module,----,Exams,input,latch,assign
来源： https://blog.csdn.net/weixin_41683205/article/details/121346228