2021-10-25
作者：互联网
FPGA## verilog中的系统函数
1.
d
i
s
p
l
a
y
2.
display 2.
display2.fopen
3.
f
c
l
o
s
e
4.
fclose 4.
fclose4.random
5.
f
w
r
i
t
e
6.
fwrite 6.
fwrite6.stop
7.$finish
http://mp.weixin.qq.com/s?__biz=Mzg3NDY5NDg5MQ==&mid=2247483670&idx=1&sn=55fbf1302df80ab517499083d0d493ef&chksm=cecd9092f9ba1984a44f5bd9d23d2bc5f7bc5846f2ccfdd4d4337674efca578b2c211125f419#rd
标签：__,10,25,##,chksm,random,fclose,mid,2021 来源： https://blog.csdn.net/qq_43111943/article/details/120960342