module top_module( 
    input a, b, sel,
    output out ); 
    always @(*)begin
        case(sel)
            0:out = a;
            1:out = b;
        endcase
    end
endmodule

062_2-to-1 Bus Multiplexer

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    always @(*)begin
        case(sel)
            0:out = a;
            1:out = b;
        endcase
    end
endmodule

063_9-to-1 Multiplexer

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always @(*)begin
        case(sel)
            0:out = a;
            1:out = b;
            2:out = c;
            3:out = d;
            4:out = e;
            5:out = f;
            6:out = g;
            7:out = h;
            8:out = i;
            default:out=16'hffff;
        endcase
    end
endmodule

064_256-to-1 Multiplexer

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
endmodule

065_256-to-1 4-Bit Multiplexer

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out = in[sel*4+3 -:4];
endmodule

7_Arithmetic Circuits

066_Half Adder

module top_module( 
    input a, b,
    output cout, sum );
    assign cout = a & b;
    assign sum = (a ^ b);
endmodule

067_Full Adder

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign sum = a^b^cin;
    assign cout = (a&b) | (a&cin) | (b&cin);
endmodule

068_3-Bit Binary Adder

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    assign sum[0]  = a[0] ^ b[0] ^ cin;
    assign cout[0] = (a[0]&b[0]) | (a[0]&cin) | (b[0]&cin);
    always @(*)begin
        for(int i=1;i<3;i++)begin
            sum[i] = a[i] ^ b[i] ^ cout[i-1];
            cout[i] = (a[i]&b[i]) | (a[i]&cout[i-1]) | (b[i]&cout[i-1]);
        end
    end
endmodule

069_Adder

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    wire [3:0] cout;
    assign  sum[0] = x[0] ^ y[0];
    assign cout[0] = x[0] & y[0];
    always @(*) begin
        for(int i=1;i<4;i++)begin
            sum[i] = x[i] ^ y[i] ^ cout[i-1];
            cout[i] = (x[i]&y[i]) | (x[i]&cout[i-1]) | (cout[i-1]&y[i]);
        end
        sum[4] = cout[3];
    end
endmodule

070_Signed Addition Overflow

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
    wire [7:0] c;
    assign s[0] = a[0] ^ b[0];
    assign c[0] = a[0] & b[0];
    always @(*) begin
        for(int i=1;i<8;i++)begin
            s[i] = a[i] ^ b[i] ^ c[i-1];
            c[i] = (a[i]&b[i]) | (a[i]&c[i-1]) | (b[i]&c[i-1]);
        end
        overflow = (a[7]&b[7]&~s[7]) | (~a[7]&~b[7]&s[7]);
    end
endmodule

071_100-Bit Binary Adder

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    wire[99:0] cout1;
    assign sum[0]  = a[0] ^ b[0] ^ cin;
    assign cout1[0] = (a[0]&b[0]) | (a[0]&cin) | (b[0]&cin);
     always @(*)begin
         for(int i=1;i<100;i++)begin
              sum[i] = a[i] ^ b[i] ^ cout1[i-1];
             cout1[i] = (a[i]&b[i]) | (a[i]&cout1[i-1]) | (b[i]&cout1[i-1]);
        end
         cout = cout1[99];
    end
endmodule

072_4-Digital BCD Adder

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    
    wire [15:0] cout_tmp;
    bcd_fadd fadd(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout_tmp[0]), .sum(sum[3:0]));
    assign cout = cout_tmp[12];
    generate
        genvar i;
        for(i = 4; i < 16; i = i + 4) begin:adder
            bcd_fadd fadd(.a(a[i+3:i]), .b(b[i+3:i]), .cin(cout_tmp[i-4]), .cout(cout_tmp[i]), .sum(sum[i+3:i]));
        end
    endgenerate
endmodule
//有点没给我整明白

8_Karmaugh Map to Circuit

073_3-Variable

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    assign out = a|b|c;
endmodule

074_4-Variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = (~b&~c) | (~a&~d) | (b&c&d) | (a&~b&d);
endmodule

075_4-Variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = a | (~b&c);
endmodule

076_4-Variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = (~a&~b&~c&d)|(~a&~b&c&~d)|(~a&b&~c&~d)|(~a&b&c&d)|(a&b&~c&d)|(a&b&c&~d)|(a&~b&~c&~d)|(a&~b&c&d);
endmodule

077_Minimum SOP And POS

A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    assign out_sop = (c&d) | (~a&~b&c);
    assign out_pos = c & (~b|d) & (d|~a);
endmodule
//pos:product-of-sums form
//sop: sum-of-products form

078_Karnaugh Map

module top_module (
    input [4:1] x, 
    output f );
    assign f = (~x[1]&x[3]) | (x[1]&x[2]&~x[3]);
endmodule

079_Karnaugh Map

module top_module (
    input [4:1] x,
    output f
); 
    assign f = (~x[1]&x[3]) | (~x[2]&~x[4]) | (x[2]&x[3]&x[4]);
endmodule

080_K-map Implemented With A Multiplexer

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    assign mux_in[0] = c | d;
    assign mux_in[1] = 0;
    assign mux_in[3] = c & d;
    assign mux_in[2] = ~d;
endmodule

标签：Circuits,top,HDLBitsLOG,module,output,input,assign,out
来源： https://blog.csdn.net/LLeetion/article/details/118735716