常用FPGA功能块记录

//runing flag led
reg[23:0]led_count = 24'd0;
always @ (posedge clk_25m or negedge rst_n) begin
    if(~rst_n)begin
        led_count <= 24'd0;
        led <= 1'b0;
    end
    else if(led_count < 24'd12_50_00_00) begin
        led_count <= led_count + 1'b1;
    end
    else begin
        led_count <= 24'd0;
        led <= ~led;
    end
end
//Watch Dog(WTD)
//25M clk  2s reset
//state1:上电等待CPU启动完成，仅在产品上电执行一次,上电复位或外部系统复位或reboot复位完成后等待1min
//state2:根据CPU配置开始看门狗计时，默认2s超时复位
//note：使能看门狗后如要禁用，先喂狗一次再进行禁用操作，防止在看门狗超时临界处操作。
wire w_FD_WTD;//input  CPU喂狗信号，高（电平）脉冲有效
reg r_WTD_Rstn;//output  看门狗复位信号，超时未喂狗拉低
wire WTD_En;//input  CPU看门狗使能信号，高有效
localparam [23:0]Param_25M_500ms = 24'hbe_bc_20;
localparam [7:0]Count_500ms_2Min = 8'hf0;
reg [23:0]Count_25M_500ms;
reg [15:0]Count_500ms_num;
//500ms计数
always @(posedge clk_25m or negedge rst_n) begin
    if(~rst_n)begin
        Count_25M_500ms <= 24'd0;
        Count_500ms_num <= 16'd0;
    end
    else if(Count_25M_500ms >= Param_25M_500ms)begin
        Count_25M_500ms <= 24'd0;
        Count_500ms_num <= Count_500ms_num + 1'b1;
    end
    else begin
        Count_25M_500ms <= Count_25M_500ms + 1'b1;
    end
end
//state machine
localparam [3:0]CPU_Startup = 4'b00_00;
localparam [3:0]CPU_Running = 4'b00_01;
localparam [3:0]CPU_WTD_Run = 4'b00_10;
reg [3:0]WTD_state = 4'b00_00;

//WTD function
reg [27:0]WTD_Count;
localparam [27:0]WTD_Count_2s = 28'd50_00_00_00;
always @ (posedge clk_25m) begin
    case(WTD_state)
        CPU_Startup:begin//do nothing
            if(Count_500ms_num <= Count_500ms_2Min)begin
                WTD_state <= CPU_Startup;
            end
            else begin
                WTD_state <= CPU_Running;
            end
        end
        CPU_Running:begin//Waite WTD Enable
            if(WTD_En) begin//WTD_En From CPU Ctr
                WTD_state <= CPU_WTD_Run;
            end
            else begin
                WTD_state <= CPU_Running;
            end
        end
        CPU_WTD_Run:begin
            if(WTD_En) begin
                WTD_state <= CPU_WTD_Run;
            end
            else begin
                WTD_state <= CPU_Running;    
            end
        end
        default:begin
            WTD_state <= CPU_Startup;
        end
    endcase
end    
always @ (posedge clk_25m) begin
    case(WTD_state)
        CPU_WTD_Run:begin
            if(w_FD_WTD)begin//feed watch dog
                WTD_Count <= 28'd0;
                r_WTD_Rstn <= 1'b1;
            end
            else begin 
                if(WTD_Count <= WTD_Count_2s)begin
                    WTD_Count <= WTD_Count + 1'b1;
                    r_WTD_Rstn <= 1'b1;
                end
                else begin
                    r_WTD_Rstn <= 1'b0;
                end
            end
        end
        default:begin
            r_WTD_Rstn <= 1'b1;
            WTD_Count <= 28'd0;
        end
    endcase
end

标签：count,begin,led,FPGA,记录,25M,rst,功能块,500ms
来源： https://www.cnblogs.com/dlutccj/p/14903152.html