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下降沿触发

作者:互联网

always @ (posedge clk or negedge resetn)  
    if (!resetn) r_vsync <= `SD 1'b0;   
    else         r_vsync <= `SD vsync;
wire vsync_fe = (!vsync)&r_vsync;
always @ (posedge clk or negedge resetn)begin
     if (!resetn) 
         xxxx;
     else if (vsync_fe)
         xxx <= xxx;
end

标签:触发,posedge,clk,always,negedge,resetn,下降,vsync
来源: https://blog.csdn.net/weixin_43475286/article/details/117520218